Design-For-Testability of On-Chip Control in mVLSI Biochips

Seetal Potluri, Paul Pop, Jan Madsen*

*Corresponding author for this work

Research output: Contribution to journalJournal articleResearchpeer-review

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Abstract

To enable mVLSI biochips for point-of-care applications, recent work has focused on reducing the number of off-chip pressure sources, using on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Since these on-chip pneumatic control logic circuits in turn control the fluidic operations, it is very important that they are fault-free, in order to avoid the failure of biochemical applications. For the first time, this paper proposes a design-fortestability (DFT) scheme to test for faults inside on-chip pneumatic control logic circuits, by adding observation pneumatic latches into the circuit.
Original languageEnglish
JournalI E E E Design & Test
Volume36
Issue number1
Pages (from-to)48-56
Number of pages6
ISSN2168-2356
DOIs
Publication statusPublished - 2019

Keywords

  • mVLSI biochips
  • On-Chip Control
  • Manufacturing defects
  • Design-For-Testability

Cite this

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title = "Design-For-Testability of On-Chip Control in mVLSI Biochips",
abstract = "To enable mVLSI biochips for point-of-care applications, recent work has focused on reducing the number of off-chip pressure sources, using on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Since these on-chip pneumatic control logic circuits in turn control the fluidic operations, it is very important that they are fault-free, in order to avoid the failure of biochemical applications. For the first time, this paper proposes a design-fortestability (DFT) scheme to test for faults inside on-chip pneumatic control logic circuits, by adding observation pneumatic latches into the circuit.",
keywords = "mVLSI biochips, On-Chip Control, Manufacturing defects, Design-For-Testability",
author = "Seetal Potluri and Paul Pop and Jan Madsen",
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Design-For-Testability of On-Chip Control in mVLSI Biochips. / Potluri, Seetal; Pop, Paul; Madsen, Jan.

In: I E E E Design & Test, Vol. 36, No. 1, 2019, p. 48-56.

Research output: Contribution to journalJournal articleResearchpeer-review

TY - JOUR

T1 - Design-For-Testability of On-Chip Control in mVLSI Biochips

AU - Potluri, Seetal

AU - Pop, Paul

AU - Madsen, Jan

PY - 2019

Y1 - 2019

N2 - To enable mVLSI biochips for point-of-care applications, recent work has focused on reducing the number of off-chip pressure sources, using on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Since these on-chip pneumatic control logic circuits in turn control the fluidic operations, it is very important that they are fault-free, in order to avoid the failure of biochemical applications. For the first time, this paper proposes a design-fortestability (DFT) scheme to test for faults inside on-chip pneumatic control logic circuits, by adding observation pneumatic latches into the circuit.

AB - To enable mVLSI biochips for point-of-care applications, recent work has focused on reducing the number of off-chip pressure sources, using on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Since these on-chip pneumatic control logic circuits in turn control the fluidic operations, it is very important that they are fault-free, in order to avoid the failure of biochemical applications. For the first time, this paper proposes a design-fortestability (DFT) scheme to test for faults inside on-chip pneumatic control logic circuits, by adding observation pneumatic latches into the circuit.

KW - mVLSI biochips

KW - On-Chip Control

KW - Manufacturing defects

KW - Design-For-Testability

U2 - 10.1109/MDAT.2018.2873448

DO - 10.1109/MDAT.2018.2873448

M3 - Journal article

VL - 36

SP - 48

EP - 56

JO - I E E E Design & Test

JF - I E E E Design & Test

SN - 2168-2356

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