Design-For-Testability of On-Chip Control in mVLSI Biochips

To enable mVLSI biochips for point-of-care applications, recent work has focused on reducing the number of off-chip pressure sources, using on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Since these on-chip pneumatic control logic circuits in turn control the fluidic operations, it is very important that they are fault-free, in order to avoid the failure of biochemical applications. For the first time, this paper proposes a design-fortestability (DFT) scheme to test for faults inside on-chip pneumatic control logic circuits, by adding observation pneumatic latches into the circuit.