Abstract
This article contains the problem statement and numerical estimations regarding design of high-performance Time Sensitive Networking (TSN) switching nodes. Performance metrics and delay components are introduced and the impact of each design choice on them is investigated. An architecture supporting the TSN features of Credit Based Shaping (CBS) and Time Aware Shaper (TAS) in a high-performance input queued switch is presented, together with supporting scheduling algorithm. The paper additionally contains a set of recommendations for design of high-capacity TSN switches.
| Original language | English |
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| Title of host publication | Proceedings of 2019 10th International Conference on Networks of the Future |
| Publisher | IEEE |
| Publication date | 2019 |
| Pages | 114-117 |
| ISBN (Print) | 9781728144443 |
| DOIs | |
| Publication status | Published - 2019 |
| Event | 10th International Conference on the Network of the Future - Engineering Faculty of University of Rome "La Sapienza", Rome, Italy Duration: 1 Oct 2019 → 3 Oct 2019 Conference number: 10 |
Conference
| Conference | 10th International Conference on the Network of the Future |
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| Number | 10 |
| Location | Engineering Faculty of University of Rome "La Sapienza" |
| Country/Territory | Italy |
| City | Rome |
| Period | 01/10/2019 → 03/10/2019 |
Keywords
- Ethernet
- TSN
- Scheduling
- Queuing
- Delay
- Switching
- QoS
- Quality of service
- Input queuing