Design considerations for high-performance Time Sensitive Networking switches

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

This article contains the problem statement and numerical estimations regarding design of high-performance Time Sensitive Networking (TSN) switching nodes. Performance metrics and delay components are introduced and the impact of each design choice on them is investigated. An architecture supporting the TSN features of Credit Based Shaping (CBS) and Time Aware Shaper (TAS) in a high-performance input queued switch is presented, together with supporting scheduling algorithm. The paper additionally contains a set of recommendations for design of high-capacity TSN switches.
Original languageEnglish
Title of host publicationProceedings of 2019 10th International Conference on Networks of the Future
PublisherIEEE
Publication date2019
Pages114-117
ISBN (Print)9781728144443
DOIs
Publication statusPublished - 2019
Event2019 10th International Conference on the Network of the Future - Engineering Faculty of University of Rome "La Sapienza", Rome, Italy
Duration: 1 Oct 20193 Oct 2019

Conference

Conference2019 10th International Conference on the Network of the Future
LocationEngineering Faculty of University of Rome "La Sapienza"
CountryItaly
CityRome
Period01/10/201903/10/2019

Keywords

  • Ethernet
  • TSN
  • Scheduling
  • Queuing
  • Delay
  • Switching
  • QoS
  • Quality of service
  • Input queuing

Cite this

Pruski, A., & Berger, M. S. (2019). Design considerations for high-performance Time Sensitive Networking switches. In Proceedings of 2019 10th International Conference on Networks of the Future (pp. 114-117). IEEE. https://doi.org/10.1109/nof47743.2019.9014950