Design considerations for a digital audio Class D output stage with emphasis on hearing aid application

Peter Pracný

Research output: Book/ReportPh.D. thesis

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Abstract

This work deals with power optimization of the audio signal processing back end (the interpolation filter, the ΣΔ modulator and the Class D power amplifier) as a whole. Understanding of the design parameter tradeoffs is used to derive the specifications for the back end and to understand the state-of-the-art. A figure-of-merit which allows judging the power consumption of the digital part of the back end early in the design process is proposed. The insight into the tradeoffs involved is subsequently used to optimize the interpolation filter and the system-level parameters of the ΣΔ modualtor so that the switching frequency of the Class D power amplifier – the main power consumer in the back end - is minimized.
• In the multistage interpolation filter the first stage is implemented as a half-band IIR filter consisting of two parallel all-pass cells. A novel approach that does not require any rigorous numerical techniques is proposed to quantize the filter coefficients. Together with the simple all-pass cells the resulting filter has very low hardware / power demands compared to the state-of-the-art.
• The switching frequency of the Class D power amplifier is reduced at the cost of the increase of the maximum clock frequency in the digital part of the back end. This approach moves the burden from the Class D power amplifier to the digital part, which easily scales with the IC technologies of today - optimized for digital design.
• Judging by the figure-of-merit five design iterations are performed that lower the power consumption of the interpolation filter combined with the ΣΔ modulator by 82% and the switching frequency of the Class D power amplifier by 94% compared to the initial design.
• The result is the digital part of the back end optimized with respect to power, which provides audio performance comparable to the state-of-the-art. This is combined with the lowest switching frequency of the Class D power amplifier reported in literature for the ΣΔ modulator-based digital back end.
Future work for the digital ΣΔ modulator and the power amplifier with feedback is proposed.
Original languageEnglish
PublisherTechnical University of Denmark, Department of Electrical Engineering
Number of pages140
Publication statusPublished - 2013

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