Design and verification of a self-timed RAM

Lars Skovby Nielsen; Jørgen Staunstrup

doi:10.1109/ASPDAC.1995.486398

Design and verification of a self-timed RAM

Lars Skovby Nielsen
, Jørgen Staunstrup

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This paper describes a self-timed static RAM. A single bit RAM is described in the design language SYNCHRONIZED TRANSITIONS and using the verification tools supporting this language, it is shown that the design is speed-independent. Furthermore, a transistor level implementation of the design is presented

Original language	English
Title of host publication	Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95
Publisher	IEEE
Publication date	1995
Pages	751-758
ISBN (Print)	49-30-81367-0
DOIs	https://doi.org/10.1109/ASPDAC.1995.486398
Publication status	Published - 1995
Event	Conference on Design Automation : International Conference on Hardware Description Languages; International Conference on Very Large Scale Integration. - Duration: 1 Jan 1995 → …

Conference

Conference	Conference on Design Automation : International Conference on Hardware Description Languages; International Conference on Very Large Scale Integration.
Period	01/01/1995 → …

Bibliographical note

Copyright: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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PY - 1995

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N2 - This paper describes a self-timed static RAM. A single bit RAM is described in the design language SYNCHRONIZED TRANSITIONS and using the verification tools supporting this language, it is shown that the design is speed-independent. Furthermore, a transistor level implementation of the design is presented

AB - This paper describes a self-timed static RAM. A single bit RAM is described in the design language SYNCHRONIZED TRANSITIONS and using the verification tools supporting this language, it is shown that the design is speed-independent. Furthermore, a transistor level implementation of the design is presented

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ER -

Design and verification of a self-timed RAM

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