Design and verification of a self-timed RAM

Lars Skovby Nielsen, Jørgen Staunstrup

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

    227 Downloads (Pure)

    Abstract

    This paper describes a self-timed static RAM. A single bit RAM is described in the design language SYNCHRONIZED TRANSITIONS and using the verification tools supporting this language, it is shown that the design is speed-independent. Furthermore, a transistor level implementation of the design is presented
    Original languageEnglish
    Title of host publicationProceedings of the ASP-DAC '95/CHDL '95/VLSI '95
    PublisherIEEE
    Publication date1995
    Pages751-758
    ISBN (Print)49-30-81367-0
    DOIs
    Publication statusPublished - 1995
    EventConference on Design Automation : International Conference on Hardware Description Languages; International Conference on Very Large Scale Integration. -
    Duration: 1 Jan 1995 → …

    Conference

    ConferenceConference on Design Automation : International Conference on Hardware Description Languages; International Conference on Very Large Scale Integration.
    Period01/01/1995 → …

    Bibliographical note

    Copyright: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

    Cite this

    Nielsen, L. S., & Staunstrup, J. (1995). Design and verification of a self-timed RAM. In Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95 (pp. 751-758). IEEE. https://doi.org/10.1109/ASPDAC.1995.486398