Design and performance analysis of delay insensitive multi-ring structures

Jens Sparsø; Jørgen Staunstrup

doi:10.1109/HICSS.1993.270630

Design and performance analysis of delay insensitive multi-ring structures

Jens Sparsø, Jørgen Staunstrup

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

611 Downloads (Orbit)

Abstract

A set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits is described. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm. The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the analysis elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings that are composed into larger multiring structures by joining and forking of signals. By limiting to this class of structures, it is possible, even for complex designs, to analyze the performance and establish an understanding of the bottlenecks.

Original language	English
Title of host publication	Proceeding of the 26th Hawaii International Conference on System Sciences
Volume	Volume 1
Publisher	IEEE
Publication date	1993
Pages	349-358
ISBN (Print)	08-18-63230-5
DOIs	https://doi.org/10.1109/HICSS.1993.270630
Publication status	Published - 1993
Event	Hawaii International Conference on Systems Sciences - Hawaii, US Duration: 1 Jan 1993 → …

Conference

Conference	Hawaii International Conference on Systems Sciences
City	Hawaii, US
Period	01/01/1993 → …

Bibliographical note

Copyright 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Access to Document

10.1109/HICSS.1993.270630

JensFinal published version, 962 KB

OpenUrl availability

Full text

Cite this

@inproceedings{c1a6e99cfd3b4810ba08af04358defa4,

title = "Design and performance analysis of delay insensitive multi-ring structures",

abstract = "A set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits is described. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm. The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the analysis elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings that are composed into larger multiring structures by joining and forking of signals. By limiting to this class of structures, it is possible, even for complex designs, to analyze the performance and establish an understanding of the bottlenecks.",

author = "Jens Spars{\o} and J{\o}rgen Staunstrup",

note = "Copyright 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; Hawaii International Conference on Systems Sciences, HICSS'26 ; Conference date: 01-01-1993",

year = "1993",

doi = "10.1109/HICSS.1993.270630",

language = "English",

isbn = "08-18-63230-5",

volume = "Volume 1",

pages = "349--358",

booktitle = "Proceeding of the 26th Hawaii International Conference on System Sciences",

publisher = "IEEE",

address = "United States",

}

TY - GEN

T1 - Design and performance analysis of delay insensitive multi-ring structures

AU - Sparsø, Jens

AU - Staunstrup, Jørgen

N1 - Copyright 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

PY - 1993

Y1 - 1993

N2 - A set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits is described. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm. The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the analysis elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings that are composed into larger multiring structures by joining and forking of signals. By limiting to this class of structures, it is possible, even for complex designs, to analyze the performance and establish an understanding of the bottlenecks.

AB - A set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits is described. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm. The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the analysis elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings that are composed into larger multiring structures by joining and forking of signals. By limiting to this class of structures, it is possible, even for complex designs, to analyze the performance and establish an understanding of the bottlenecks.

U2 - 10.1109/HICSS.1993.270630

DO - 10.1109/HICSS.1993.270630

M3 - Article in proceedings

SN - 08-18-63230-5

VL - Volume 1

SP - 349

EP - 358

BT - Proceeding of the 26th Hawaii International Conference on System Sciences

PB - IEEE

T2 - Hawaii International Conference on Systems Sciences

Y2 - 1 January 1993

ER -

Design and performance analysis of delay insensitive multi-ring structures

Abstract

Conference

Bibliographical note

Access to Document

OpenUrl availability

Fingerprint

Cite this