Design and performance analysis of delay insensitive multi-ring structures

Jens Sparsø, Jørgen Staunstrup

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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    Abstract

    A set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits is described. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm. The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the analysis elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings that are composed into larger multiring structures by joining and forking of signals. By limiting to this class of structures, it is possible, even for complex designs, to analyze the performance and establish an understanding of the bottlenecks.
    Original languageEnglish
    Title of host publicationProceeding of the 26th Hawaii International Conference on System Sciences
    VolumeVolume 1
    PublisherIEEE
    Publication date1993
    Pages349-358
    ISBN (Print)08-18-63230-5
    DOIs
    Publication statusPublished - 1993
    EventHawaii International Conference on Systems Sciences - Hawaii, US
    Duration: 1 Jan 1993 → …

    Conference

    ConferenceHawaii International Conference on Systems Sciences
    CityHawaii, US
    Period01/01/1993 → …

    Bibliographical note

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