Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

Kåre Tais Christensen

doi:10.1109/VLSIC.2001.934238

Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

Kåre Tais Christensen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.

Original language	English
Title of host publication	Digest of the 2001 IEEE VLSI Circuits Symposium
Place of Publication	Kyoto
Publication date	2001
ISBN (Print)	4-89114-014-3
DOIs	https://doi.org/10.1109/VLSIC.2001.934238
Publication status	Published - 2001
Event	2001 Symposium on VLSI Circuits - Kyoto, Japan Duration: 14 Jun 2001 → 16 Jun 2001

Conference

Conference	2001 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	14/06/2001 → 16/06/2001

Bibliographical note

Copyright: 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "Design and Characterization of Vertical Mesh Capacitors in Standard CMOS",

abstract = "This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6\% bottom plate capacitance, better than 3-5\% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.",

author = "Christensen, \{K{\aa}re Tais\}",

note = "Copyright: 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 2001 Symposium on VLSI Circuits ; Conference date: 14-06-2001 Through 16-06-2001",

year = "2001",

doi = "10.1109/VLSIC.2001.934238",

language = "English",

isbn = "4-89114-014-3",

booktitle = "Digest of the 2001 IEEE VLSI Circuits Symposium",

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AU - Christensen, Kåre Tais

N1 - Copyright: 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 2001

Y1 - 2001

N2 - This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.

AB - This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.

U2 - 10.1109/VLSIC.2001.934238

DO - 10.1109/VLSIC.2001.934238

M3 - Article in proceedings

SN - 4-89114-014-3

BT - Digest of the 2001 IEEE VLSI Circuits Symposium

CY - Kyoto

T2 - 2001 Symposium on VLSI Circuits

Y2 - 14 June 2001 through 16 June 2001

ER -

Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

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