Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

Kåre Tais Christensen

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    Abstract

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.
    Original languageEnglish
    Title of host publicationDigest of the 2001 IEEE VLSI Circuits Symposium
    Place of PublicationKyoto
    Publication date2001
    ISBN (Print)4-89114-014-3
    DOIs
    Publication statusPublished - 2001
    EventSymposium on VLSI Circuits - Kyoto
    Duration: 1 Jan 2001 → …

    Conference

    ConferenceSymposium on VLSI Circuits
    CityKyoto
    Period01/01/2001 → …

    Bibliographical note

    Copyright: 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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