Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.
|Title of host publication||Proceedings of the 2nd European Design Automation Conference|
|Publication status||Published - 1991|
|Event||2nd European Conference on Design Automation - Amsterdam, Netherlands|
Duration: 25 Feb 1991 → 28 Feb 1991
Conference number: 2
|Conference||2nd European Conference on Design Automation|
|Period||25/02/1991 → 28/02/1991|