Delay estimation for CMOS functional cells

Jan Madsen

doi:10.1109/EDAC.1991.206369

Delay estimation for CMOS functional cells

Jan Madsen

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.

Original language	English
Title of host publication	Proceedings of the 2nd European Design Automation Conference
Publisher	IEEE
Publication date	1991
DOIs	https://doi.org/10.1109/EDAC.1991.206369
Publication status	Published - 1991
Event	2nd European Conference on Design Automation - Amsterdam, Netherlands Duration: 25 Feb 1991 → 28 Feb 1991 Conference number: 2 http://ieeexplore.ieee.org/xpl/tocresult.jsp?sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A5284%29&rowsPerPage=100&pageNumber=1&resultAction=ROWS_PER_PAGE

Conference

Conference	2nd European Conference on Design Automation
Number	2
Country/Territory	Netherlands
City	Amsterdam
Period	25/02/1991 → 28/02/1991
Internet address	http://ieeexplore.ieee.org/xpl/tocresult.jsp?sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A5284%29&rowsPerPage=100&pageNumber=1&resultAction=ROWS_PER_PAGE

Bibliographical note

Copyright 1991 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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title = "Delay estimation for CMOS functional cells",

abstract = "Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.",

author = "Jan Madsen",

note = "Copyright 1991 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 2nd European Conference on Design Automation, EDAC-91 ; Conference date: 25-02-1991 Through 28-02-1991",

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AB - Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.

U2 - 10.1109/EDAC.1991.206369

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M3 - Article in proceedings

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Delay estimation for CMOS functional cells

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