Delay estimation for CMOS functional cells

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    Abstract

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment.
    Original languageEnglish
    Title of host publicationProceedings of the 2nd European Design Automation Conference
    PublisherIEEE
    Publication date1991
    DOIs
    Publication statusPublished - 1991
    Event2nd European Conference on Design Automation - Amsterdam, Netherlands
    Duration: 25 Feb 199128 Feb 1991
    Conference number: 2
    http://ieeexplore.ieee.org/xpl/tocresult.jsp?sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A5284%29&rowsPerPage=100&pageNumber=1&resultAction=ROWS_PER_PAGE

    Conference

    Conference2nd European Conference on Design Automation
    Number2
    CountryNetherlands
    CityAmsterdam
    Period25/02/199128/02/1991
    Internet address

    Bibliographical note

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