Degrading Precision Arithmetics for Low-power FIR Implementation

Pietro Albicocco (Invited author), Gian Carlo Cardarilli (Invited author), Alberto Nannarelli (Invited author), Massimo Petricca (Invited author), Marco Re (Invited author)

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

    Abstract

    In this paper a review of different techniques used to implement highly optimized DSP systems is presented. The case of study is the implementation of parallel FIR filters aimed to applications characterized by high speed and high selectivity in frequency where at the same time low power dissipation is mandatory. After a review of the possible "standard" optimization techniques, the paper addresses aggressive methodologies where power and area savings are obtained by introducing the concept of "Degrading Precision Arithmetic" (DPA). Three different approaches are discussed: DPA-I, based on selective bit freezing, DPA-II, based on VDD voltage scaling, and DPA-III, based on power gating. Some theoreticaVsimuiative analysis of the introduced arithmetic errors and some implementation results are shown. A discussion on the suitability of these methodologies on standard cell technologies and FPGAs is also addressed. In our experience, these techniques are well known in the scientific community, but they are not extensively known in the design communiy, and, consequently, they are scarcely utilized.
    Original languageEnglish
    Title of host publication2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
    PublisherIEEE
    Publication date2011
    ISBN (Print)978-1-61284-856-3
    ISBN (Electronic)978-1-61284-855-6
    DOIs
    Publication statusPublished - 2011
    Event54th IEEE International Midwest Symposium on Circuits and Systems - Seoul, Korea, Democratic People's Republic of
    Duration: 7 Aug 201110 Aug 2011
    Conference number: 54
    http://www.ieee.org/conferences_events/conferences/conferencedetails/index.html?Conf_ID=17623

    Conference

    Conference54th IEEE International Midwest Symposium on Circuits and Systems
    Number54
    CountryKorea, Democratic People's Republic of
    CitySeoul
    Period07/08/201110/08/2011
    Internet address
    SeriesMidwest Symposium on Circuits and Systems. Conference Proceedings
    ISSN1548-3746

    Cite this

    Albicocco, P., Cardarilli, G. C., Nannarelli, A., Petricca, M., & Re, M. (2011). Degrading Precision Arithmetics for Low-power FIR Implementation. In 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) IEEE. Midwest Symposium on Circuits and Systems. Conference Proceedings https://doi.org/10.1109/MWSCAS.2011.6026265