Decimal Engine for Energy-Efficient Multicore Processors

Alberto Nannarelli

doi:10.1109/VLSI-SoC.2014.7004176

Decimal Engine for Energy-Efficient Multicore Processors

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

Prior work demonstrated the use of specialized processors, or accelerators, be energy-efficient for binary floatingpoint (BFP) division and square root, and for decimal floatingpoint (DFP) operations. In the dark silicon era, where not all the circuits on the die can be powered simultaneously, we propose a hybrid BFP/DFP engine to perform BFP division and DFP addition, multiplication and division. The main purpose of this engine is to offload the binary floating-point units for this type of operations and reduce the latency for decimal operations, and power and temperature for the whole die.

Original language	English
Title of host publication	Proceedings of the 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Number of pages	6
Publisher	IEEE
Publication date	2014
ISBN (Print)	978-1-4799-6016-3
DOIs	https://doi.org/10.1109/VLSI-SoC.2014.7004176
Publication status	Published - 2014
Event	22nd IFIP/IEEE International Conference on Very Large Scale Integration - Playa del Carmen, Mexico Duration: 6 Oct 2014 → 8 Oct 2014 Conference number: 22 http://xilonen.inaoep.mx/vlsi-soc2014/

Conference

Conference	22nd IFIP/IEEE International Conference on Very Large Scale Integration
Number	22
Country/Territory	Mexico
City	Playa del Carmen
Period	06/10/2014 → 08/10/2014
Internet address	http://xilonen.inaoep.mx/vlsi-soc2014/

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title = "Decimal Engine for Energy-Efficient Multicore Processors",

abstract = "Prior work demonstrated the use of specialized processors, or accelerators, be energy-efficient for binary floatingpoint (BFP) division and square root, and for decimal floatingpoint (DFP) operations. In the dark silicon era, where not all the circuits on the die can be powered simultaneously, we propose a hybrid BFP/DFP engine to perform BFP division and DFP addition, multiplication and division. The main purpose of this engine is to offload the binary floating-point units for this type of operations and reduce the latency for decimal operations, and power and temperature for the whole die.",

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note = "22nd IFIP/IEEE International Conference on Very Large Scale Integration , VLSI-SoC ; Conference date: 06-10-2014 Through 08-10-2014",

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AB - Prior work demonstrated the use of specialized processors, or accelerators, be energy-efficient for binary floatingpoint (BFP) division and square root, and for decimal floatingpoint (DFP) operations. In the dark silicon era, where not all the circuits on the die can be powered simultaneously, we propose a hybrid BFP/DFP engine to perform BFP division and DFP addition, multiplication and division. The main purpose of this engine is to offload the binary floating-point units for this type of operations and reduce the latency for decimal operations, and power and temperature for the whole die.

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DO - 10.1109/VLSI-SoC.2014.7004176

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PB - IEEE

T2 - 22nd IFIP/IEEE International Conference on Very Large Scale Integration

Y2 - 6 October 2014 through 8 October 2014

ER -

Decimal Engine for Energy-Efficient Multicore Processors

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