Decimal Engine for Energy-Efficient Multicore Processors

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Abstract

Prior work demonstrated the use of specialized processors, or accelerators, be energy-efficient for binary floatingpoint (BFP) division and square root, and for decimal floatingpoint (DFP) operations. In the dark silicon era, where not all the circuits on the die can be powered simultaneously, we propose a hybrid BFP/DFP engine to perform BFP division and DFP addition, multiplication and division. The main purpose of this engine is to offload the binary floating-point units for this type of operations and reduce the latency for decimal operations, and power and temperature for the whole die.
Original languageEnglish
Title of host publicationProceedings of the 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Number of pages6
PublisherIEEE
Publication date2014
ISBN (Print)978-1-4799-6016-3
DOIs
Publication statusPublished - 2014
Event22nd IFIP/IEEE International Conference on Very Large Scale Integration - Playa del Carmen, Mexico
Duration: 6 Oct 20148 Oct 2014
Conference number: 22
http://xilonen.inaoep.mx/vlsi-soc2014/

Conference

Conference22nd IFIP/IEEE International Conference on Very Large Scale Integration
Number22
CountryMexico
CityPlaya del Carmen
Period06/10/201408/10/2014
Internet address

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