Custom Topology Generation for Network-on-Chip

Matthias Bo Stuart; Jens Sparsø

doi:10.1109/NORCHP.2007.4481044

Custom Topology Generation for Network-on-Chip

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration around an initial topology. The tabu search has been modified from its normally encountered form to allow easier escaping from local minima. A number of synthetic benchmarks are used for tuning the parameters of both heuristics and for testing the quality of the solutions each heuristic produces. An analytical model is used to determine communication latencies in the network-on-chip.

Original language	English
Title of host publication	25th IEEE Norchip Conference
Publisher	IEEE
Publication date	2007
Pages	1-4
ISBN (Print)	978-1-4244-1516-8
DOIs	https://doi.org/10.1109/NORCHP.2007.4481044
Publication status	Published - 2007
Event	2007 IEEE 25th NORCHIP Conference - Aalborg, Denmark Duration: 19 Nov 2007 → 20 Nov 2007 Conference number: 25 https://ieeexplore.ieee.org/xpl/conhome/4472911/proceeding

Conference

Conference	2007 IEEE 25th NORCHIP Conference
Number	25
Country/Territory	Denmark
City	Aalborg
Period	19/11/2007 → 20/11/2007
Internet address	https://ieeexplore.ieee.org/xpl/conhome/4472911/proceeding

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10.1109/NORCHP.2007.4481044

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@inproceedings{8d75c86bdb534b81b7e70439090f4e47,

title = "Custom Topology Generation for Network-on-Chip",

abstract = "This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration around an initial topology. The tabu search has been modified from its normally encountered form to allow easier escaping from local minima. A number of synthetic benchmarks are used for tuning the parameters of both heuristics and for testing the quality of the solutions each heuristic produces. An analytical model is used to determine communication latencies in the network-on-chip.",

author = "Stuart, \{Matthias Bo\} and Jens Spars{\o}",

year = "2007",

doi = "10.1109/NORCHP.2007.4481044",

language = "English",

isbn = "978-1-4244-1516-8",

pages = "1--4",

booktitle = "25th IEEE Norchip Conference",

publisher = "IEEE",

address = "United States",

note = "2007 IEEE 25th NORCHIP Conference ; Conference date: 19-11-2007 Through 20-11-2007",

url = "https://ieeexplore.ieee.org/xpl/conhome/4472911/proceeding",

}

TY - GEN

T1 - Custom Topology Generation for Network-on-Chip

AU - Stuart, Matthias Bo

AU - Sparsø, Jens

N1 - Conference code: 25

PY - 2007

Y1 - 2007

N2 - This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration around an initial topology. The tabu search has been modified from its normally encountered form to allow easier escaping from local minima. A number of synthetic benchmarks are used for tuning the parameters of both heuristics and for testing the quality of the solutions each heuristic produces. An analytical model is used to determine communication latencies in the network-on-chip.

AB - This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration around an initial topology. The tabu search has been modified from its normally encountered form to allow easier escaping from local minima. A number of synthetic benchmarks are used for tuning the parameters of both heuristics and for testing the quality of the solutions each heuristic produces. An analytical model is used to determine communication latencies in the network-on-chip.

U2 - 10.1109/NORCHP.2007.4481044

DO - 10.1109/NORCHP.2007.4481044

M3 - Article in proceedings

SN - 978-1-4244-1516-8

SP - 1

EP - 4

BT - 25th IEEE Norchip Conference

PB - IEEE

T2 - 2007 IEEE 25th NORCHIP Conference

Y2 - 19 November 2007 through 20 November 2007

ER -

Custom Topology Generation for Network-on-Chip

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