Custom Topology Generation for Network-on-Chip

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    Abstract

    This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration around an initial topology. The tabu search has been modified from its normally encountered form to allow easier escaping from local minima. A number of synthetic benchmarks are used for tuning the parameters of both heuristics and for testing the quality of the solutions each heuristic produces. An analytical model is used to determine communication latencies in the network-on-chip.
    Original languageEnglish
    Title of host publication25th IEEE Norchip Conference
    PublisherIEEE
    Publication date2007
    Pages1-4
    ISBN (Print)978-1-4244-1516-8
    DOIs
    Publication statusPublished - 2007
    Event25th IEEE Norchip Conference - Aalborg, Denmark
    Duration: 19 Nov 200720 Nov 2007
    Conference number: 25

    Conference

    Conference25th IEEE Norchip Conference
    Number25
    CountryDenmark
    CityAalborg
    Period19/11/200720/11/2007

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