Custom Integrated Circuit Design for Portable Ultrasound Scanners

This work concerns the integrated circuitry contained inside a portable ultrasound scanner. These scanners are size and power limited, therefore, the main challenge is to achieve an acceptable picture quality within those restrictions. The structure of portable ultrasound scanners is different from traditional static ultrasound scanners since the data acquired is pre-beamformed, and thereby reduced, in the handheld probe. As a result, the circuitry inside the handheld probe is complex and is required to be small and efficient. Furthermore, it needs to reach enough performance to generate a usable picture quality, within the area and power budget limitations.
A handheld probe for portable ultrasound scanners contains several transducers, trans-mitting channels and receiving channels. In order to pre-beamform, the transmitting channels individually excite the transducers in a sequence filling the imaging plane and the signals received from each transmit burst area summed. Each receiving channel is required to individually amplify and delay its signal in order to correctly pre-beamform. The handheld probe delivers the data to a processing unit digitally, hence, analog to digital converters (ADCs) are contained in the probe.
Due to the nature of ultrasonic transducers, the transmitting circuitry needs to generate high-voltage pulses to drive them. Furthermore, the low-voltage receiving circuitry has to provide high enough signal to noise ratio (SNR) in order to generate usable imaging. For the purpose of evaluating the feasibility of the transmitting and receiving circuitry of a handheld probe for portable ultrasound scanners, three integrated circuit prototypes have been fabricated. Measurements have been performed on all of them with satisfactory results.
The first part of this project is focused on the high-voltage transmitting channels cir-cuitry. This circuitry is required to generate pulses in the range of 100 V with fre-quencies around 5 MHz. The first prototype contains a full reconfigurable single-ended transmitting channel occupying a die area of 0.938 mm2 and a power consumption of 1.41 mW. The second prototype contains a full differential transmitting channel, which has improvements on performance, smaller die area of 0.18 mm2 and lower power con-sumption of 0.936 mW.
The second part of the project aims at the receiving channel circuitry. The third proto-type includes a continuous-time delta-sigma analog-to-digital converter (CTDS ADC) operating at a sampling frequency of 320 MHz, a SNR of 45 dB, occupying an area of 0.0175 mm2 and a power consumption of 0.594 mW. The CTDS ADC digitizes the signal before the pre-beamform summing is applied. The SNR of the ADC is directly linked to the picture quality of the imaging. However, the SNR is also related to the power consumption, creating a tradeoff between power and picture quality. The design approach will be to achieve the minimum SNR that generates an acceptable picture quality while using the minimum power possible. The ADC is implemented as an over-sampled data converter with 1-bit output in order to simplify the accurate digital delay needed in each receiving channel to pre-beamform. Using this approach, the digital delay can be very efficiently implemented as an inverter based digital delay line with switches, achieving accurate precise delay that scales with technology.