Current Mode Data Converters for Sensor Systems

This thesis is mainly concerned with data conversion. Especially data conversion using current mode signal processing is treated.A tutorial chapter introducing D/A conversion is presented. In this chapter the effects that cause static and dynamic nonlinearities are discussed along with methods to reduce these. A novel measure called the 'error energy measure' is presented. This measure is very helpful in the design phase as it evaluates the dynamic performance of a DAC without performing long term simulations. A thorough analysis of the stability of 1-bit oversampled data converters is presented. Also, a methodology for designing the feedback filter in oversampled data converters is presented. Finally, the effect of nonideal effects in oversampled converters is investigated.Switched current (SI) technique is briefly presented at the system level and transistor level. A thorough analysis of noise in SI is presented which leads to a new optimization methodology for SI. The optimization methodology minimizes the power consumption for a given performance (SNR and THD). The optimization methodology also takes process variations into account.Six chips have been implemented based on the theory in the thesis. An analog multiplierless adaptive filter that estimates the delay in a microflow channel is implemented using SI technique. A thorough analysis shows that this methodology results in a system that is invariant to nonlinearities in the flow channel and in the signal conditioner preceeding the adaptive filter. This is utilized to quantize the input signals to the adaptive filter into one bit, which means that all multipliers can be replaced by switches and thus the hardware complexity is significantly reduced.Three high speed DACs based on the current steering principle are implemented using a 0.8 micron BiCMOS process. The performance of the first DAC presented is a SFDR of 43dB for a generated frequency of approximately 30MHz and at a sampling rate of 100MSamples/s. The SFDR is 50dB for a generated frequency of approximately 10MHz. The maximum conversion rate is 140MSamples/s. The second DAC performs slightly poorer than the first one and the third DAC does not operate properly.A third order SI A/D Sigma-Delta modulator is presented. A thorough analysis is presented that shows that the design of the modulator at the system level and the SI building blocks at the transistor level must be treated as a whole. It is shown that an optimal choice of modulator architecture exists with respect to power consumption. A thorough noise analysis is presented and the power consumption for the modulator is minimized using the optimization methodology developed for SI circuits. The modulator has a SNR of 74.5dB for a signal bandwidth of 5.5kHz and a sampling rate of 600kHz. The modulator does not enter uncontrolled oscillations when input amplitudes higher than the maximum stable amplitude are applied due to the clamping in the SI integrators in the modulator. This also means that the modulator enters a steady state when the large input amplitude is removed.Finally, a SI delay line consisting of 12 cascaded CCOPs has been processed to verify the noise analysis for the SI circuits presented. The power spectral density for the circuit is calculated and verified by measurements. In order to distinguish the power of the sampled and held noise from all other noise sources, a new measurement technique is presented. Using this technique it is found that the measured power spectral density of the sampled noise corresponds very well with the expected power spectral density.