The basic algorithms underlying an automatic hardware synthesis environment using fully formal graphical requirements specifications as source language are outlined. The source language is real-time symbolic timing diagrams [FeyerabendJosko97], which are a metric-time temporal logic such that hard real-time constraints have to be dealt with. While automata-theoretic methods based on translating the specification to a finite automaton and constructing a winning strategy in the resulting omega-regular game could in principle be used, and do indeed provide the core algorithm, complexity withstands practical application of these methods. Therefore, a compositional extension is explored, which yields modular synthesis of multi-component controllers. Based on this, a second extension is proposed for efficiently dealing with hard real-time constraints.
|Title of host publication||Formal Techniques in Real-Time and Fault-Tolerant Systems. 5th International Symposium, FTRTFT'98. Proceedings|
|ISBN (Print)||3 540 65003 2|
|Publication status||Published - 1998|
|Event||5th International Symposium Formal Techniques in Real-Time and Fault-Tolerant Systems - Kgs. Lyngby, Denmark|
Duration: 14 Sep 1998 → 18 Sep 1998
Conference number: 5
|Conference||5th International Symposium Formal Techniques in Real-Time and Fault-Tolerant Systems|
|Period||14/09/1998 → 18/09/1998|
Fränzle, M., Lüth, K., Ravn, A. P. (Ed.), & Rischel, H. (Ed.) (1998). Compiling graphical real-time specifications into silicon. In Formal Techniques in Real-Time and Fault-Tolerant Systems. 5th International Symposium, FTRTFT'98. Proceedings (pp. 272-281). Springer Verlag.