In SMECY, we believe that an efficient tool chain could only be defined when the type of parallelism required by an application domain and the hardware architecture is fixed. Furthermore, we believe that once a set of tools is available, it is possible with reasonable effort to change hardware architectures or change the type of parallelism exploited.
Mottin, J., Pacull, F., Keryell, R., & Schleuniger, P. (2014). Compilation Tool Chains and Intermediate Representations. In Smart Multicore Embedded Systems (pp. 21-32). Springer. https://doi.org/10.1007/978-1-4614-8800-2_2