### Abstract

Original language | English |
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Title of host publication | Combinational Logic-Level Verification using Boolean Expression Diagrams |

Publication date | 1997 |

Publication status | Published - 1997 |

Event | 3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design - Oxford, United Kingdom Duration: 19 Sep 1997 → 20 Sep 1997 Conference number: 3 |

### Conference

Conference | 3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design |
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Number | 3 |

Country | United Kingdom |

City | Oxford |

Period | 19/09/1997 → 20/09/1997 |

### Cite this

*Combinational Logic-Level Verification using Boolean Expression Diagrams*

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*Combinational Logic-Level Verification using Boolean Expression Diagrams.*3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Oxford, United Kingdom, 19/09/1997.

**Combinational Logic-Level Verification using Boolean
Expression Diagrams.** / Hulgaard, Henrik; Williams, Poul Frederick; Andersen, Henrik Reif.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - Combinational Logic-Level Verification using Boolean Expression Diagrams

AU - Hulgaard, Henrik

AU - Williams, Poul Frederick

AU - Andersen, Henrik Reif

PY - 1997

Y1 - 1997

N2 - Boolean Expression Diagrams (BEDs) is a new data structure for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) that are capable of representing any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. This paper demonstrates that BEDs are well suited for solving the combinational logic-level verification problem which is, given two combinational circuits, to determine whether they implement the same Boolean functions. Based on all combinational circuits in the ISCAS 85 and LGSynth 91 benchmarks, we demonstrate that BEDs outperform both standard BDD approaches and the techniques specifically developed to exploit structural similarities for efficiently solving the problem.

AB - Boolean Expression Diagrams (BEDs) is a new data structure for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) that are capable of representing any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. This paper demonstrates that BEDs are well suited for solving the combinational logic-level verification problem which is, given two combinational circuits, to determine whether they implement the same Boolean functions. Based on all combinational circuits in the ISCAS 85 and LGSynth 91 benchmarks, we demonstrate that BEDs outperform both standard BDD approaches and the techniques specifically developed to exploit structural similarities for efficiently solving the problem.

M3 - Article in proceedings

BT - Combinational Logic-Level Verification using Boolean Expression Diagrams

ER -