A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed.
|Title of host publication||Proc. IEEE International Symposium on Circuits and Systems|
|Place of Publication||Piscataway|
|Publication status||Published - 1998|
|Event||1998 IEEE International Symposium on Circuits and Systems - Monterey, CA, United States|
Duration: 31 May 1998 → 3 Jun 1998
|Conference||1998 IEEE International Symposium on Circuits and Systems|
|Period||31/05/1998 → 03/06/1998|