Clocking Scheme for Switched-Capacitor Circuits

Jesper Steensgaard-Madsen

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

    Abstract

    A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed.
    Original languageEnglish
    Title of host publicationProc. IEEE International Symposium on Circuits and Systems
    Place of PublicationPiscataway
    PublisherIEEE
    Publication date1998
    Pages488-491
    Publication statusPublished - 1998
    Event1998 IEEE International Symposium on Circuits and Systems - Monterey, CA, United States
    Duration: 31 May 19983 Jun 1998
    http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5627

    Conference

    Conference1998 IEEE International Symposium on Circuits and Systems
    CountryUnited States
    CityMonterey, CA
    Period31/05/199803/06/1998
    Internet address

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