Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller

Flemming Hansen; C.A.T. Salama

doi:10.1109/ISCAS.1996.541949

Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller

Flemming Hansen, C.A.T. Salama

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

A Clock- and Data-Recovery (CDR) IC for a Physical Layer Controller in an Asynchronous Transfer Mode (ATM) system operating at a bit rate of 2.488 Gb/s is presented. The circuit was designed and fabricated in a 0.8 μm BiCMOS process featuring 13 GHz fT bipolar transistors. Clock-recovery is accomplished with a Phase-Locked Loop (PLL). The PLL uses a Phase- and Frequency Detector (PFD) to increase the pull-in range. No external components are required. A novel Voltage Controlled Oscillator (VCO) generating both in-phase and quadrature clocks, required by the PFD, is presented. The CDR includes a 1:8 demultiplexer with bit-rotation. Emitter Coupled Logic (ECL) is used in the PLL, data-regeneration and part of the demultiplexer, while the low-speed parts of the demultiplexer are implemented in dynamic CMOS using the True Single-Phased Clock (TSPC) approach

Original language	English
Title of host publication	Proceedings of the IEEE International Symposium on Circuits and Systems : Connecting the World
Volume	Volume 4
Publisher	IEEE
Publication date	1996
Pages	125-128
ISBN (Print)	07-80-33073-0
DOIs	https://doi.org/10.1109/ISCAS.1996.541949
Publication status	Published - 1996
Event	1996 IEEE International Symposium on Circuits and Systems - Atlanta, GA, United States Duration: 12 May 1996 → 15 May 1996 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834

Conference

Conference	1996 IEEE International Symposium on Circuits and Systems
Country/Territory	United States
City	Atlanta, GA
Period	12/05/1996 → 15/05/1996
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834

Bibliographical note

Copyright 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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title = "Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller",

abstract = "A Clock- and Data-Recovery (CDR) IC for a Physical Layer Controller in an Asynchronous Transfer Mode (ATM) system operating at a bit rate of 2.488 Gb/s is presented. The circuit was designed and fabricated in a 0.8 μm BiCMOS process featuring 13 GHz fT bipolar transistors. Clock-recovery is accomplished with a Phase-Locked Loop (PLL). The PLL uses a Phase- and Frequency Detector (PFD) to increase the pull-in range. No external components are required. A novel Voltage Controlled Oscillator (VCO) generating both in-phase and quadrature clocks, required by the PFD, is presented. The CDR includes a 1:8 demultiplexer with bit-rotation. Emitter Coupled Logic (ECL) is used in the PLL, data-regeneration and part of the demultiplexer, while the low-speed parts of the demultiplexer are implemented in dynamic CMOS using the True Single-Phased Clock (TSPC) approach",

author = "Flemming Hansen and C.A.T. Salama",

note = "Copyright 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 1996 IEEE International Symposium on Circuits and Systems, ISCAS'96 ; Conference date: 12-05-1996 Through 15-05-1996",

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booktitle = "Proceedings of the IEEE International Symposium on Circuits and Systems",

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Hansen, F & Salama, CAT 1996, Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller. in Proceedings of the IEEE International Symposium on Circuits and Systems: Connecting the World. vol. Volume 4, IEEE, pp. 125-128, 1996 IEEE International Symposium on Circuits and Systems, Atlanta, GA, United States, 12/05/1996. https://doi.org/10.1109/ISCAS.1996.541949

Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller. / Hansen, Flemming; Salama, C.A.T.

Proceedings of the IEEE International Symposium on Circuits and Systems: Connecting the World. Vol. Volume 4 IEEE, 1996. p. 125-128.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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AU - Hansen, Flemming

AU - Salama, C.A.T.

N1 - Copyright 1996 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

PY - 1996

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N2 - A Clock- and Data-Recovery (CDR) IC for a Physical Layer Controller in an Asynchronous Transfer Mode (ATM) system operating at a bit rate of 2.488 Gb/s is presented. The circuit was designed and fabricated in a 0.8 μm BiCMOS process featuring 13 GHz fT bipolar transistors. Clock-recovery is accomplished with a Phase-Locked Loop (PLL). The PLL uses a Phase- and Frequency Detector (PFD) to increase the pull-in range. No external components are required. A novel Voltage Controlled Oscillator (VCO) generating both in-phase and quadrature clocks, required by the PFD, is presented. The CDR includes a 1:8 demultiplexer with bit-rotation. Emitter Coupled Logic (ECL) is used in the PLL, data-regeneration and part of the demultiplexer, while the low-speed parts of the demultiplexer are implemented in dynamic CMOS using the True Single-Phased Clock (TSPC) approach

AB - A Clock- and Data-Recovery (CDR) IC for a Physical Layer Controller in an Asynchronous Transfer Mode (ATM) system operating at a bit rate of 2.488 Gb/s is presented. The circuit was designed and fabricated in a 0.8 μm BiCMOS process featuring 13 GHz fT bipolar transistors. Clock-recovery is accomplished with a Phase-Locked Loop (PLL). The PLL uses a Phase- and Frequency Detector (PFD) to increase the pull-in range. No external components are required. A novel Voltage Controlled Oscillator (VCO) generating both in-phase and quadrature clocks, required by the PFD, is presented. The CDR includes a 1:8 demultiplexer with bit-rotation. Emitter Coupled Logic (ECL) is used in the PLL, data-regeneration and part of the demultiplexer, while the low-speed parts of the demultiplexer are implemented in dynamic CMOS using the True Single-Phased Clock (TSPC) approach

U2 - 10.1109/ISCAS.1996.541949

DO - 10.1109/ISCAS.1996.541949

M3 - Article in proceedings

SN - 07-80-33073-0

VL - Volume 4

SP - 125

EP - 128

BT - Proceedings of the IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - 1996 IEEE International Symposium on Circuits and Systems

Y2 - 12 May 1996 through 15 May 1996

ER -

Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller

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