Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller

Flemming Hansen, C.A.T. Salama

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    Abstract

    A Clock- and Data-Recovery (CDR) IC for a Physical Layer Controller in an Asynchronous Transfer Mode (ATM) system operating at a bit rate of 2.488 Gb/s is presented. The circuit was designed and fabricated in a 0.8 μm BiCMOS process featuring 13 GHz fT bipolar transistors. Clock-recovery is accomplished with a Phase-Locked Loop (PLL). The PLL uses a Phase- and Frequency Detector (PFD) to increase the pull-in range. No external components are required. A novel Voltage Controlled Oscillator (VCO) generating both in-phase and quadrature clocks, required by the PFD, is presented. The CDR includes a 1:8 demultiplexer with bit-rotation. Emitter Coupled Logic (ECL) is used in the PLL, data-regeneration and part of the demultiplexer, while the low-speed parts of the demultiplexer are implemented in dynamic CMOS using the True Single-Phased Clock (TSPC) approach
    Original languageEnglish
    Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems : Connecting the World
    VolumeVolume 4
    PublisherIEEE
    Publication date1996
    Pages125-128
    ISBN (Print)07-80-33073-0
    DOIs
    Publication statusPublished - 1996
    Event1996 IEEE International Symposium on Circuits and Systems - Atlanta, GA, United States
    Duration: 12 May 199615 May 1996
    http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834

    Conference

    Conference1996 IEEE International Symposium on Circuits and Systems
    CountryUnited States
    CityAtlanta, GA
    Period12/05/199615/05/1996
    Internet address

    Bibliographical note

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