Abstract
A Clock- and Data-Recovery (CDR) IC for a Physical Layer Controller in an Asynchronous Transfer Mode (ATM) system operating at a bit rate of 2.488 Gb/s is presented. The circuit was designed and fabricated in a 0.8 μm BiCMOS process featuring 13 GHz fT bipolar transistors. Clock-recovery is accomplished with a Phase-Locked Loop (PLL). The PLL uses a Phase- and Frequency Detector (PFD) to increase the pull-in range. No external components are required. A novel Voltage Controlled Oscillator (VCO) generating both in-phase and quadrature clocks, required by the PFD, is presented. The CDR includes a 1:8 demultiplexer with bit-rotation. Emitter Coupled Logic (ECL) is used in the PLL, data-regeneration and part of the demultiplexer, while the low-speed parts of the demultiplexer are implemented in dynamic CMOS using the True Single-Phased Clock (TSPC) approach
Original language | English |
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Title of host publication | Proceedings of the IEEE International Symposium on Circuits and Systems : Connecting the World |
Volume | Volume 4 |
Publisher | IEEE |
Publication date | 1996 |
Pages | 125-128 |
ISBN (Print) | 07-80-33073-0 |
DOIs | |
Publication status | Published - 1996 |
Event | 1996 IEEE International Symposium on Circuits and Systems - Atlanta, GA, United States Duration: 12 May 1996 → 15 May 1996 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3834 |
Conference
Conference | 1996 IEEE International Symposium on Circuits and Systems |
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Country | United States |
City | Atlanta, GA |
Period | 12/05/1996 → 15/05/1996 |
Internet address |