In this paper we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems and we find that abiologically inspired approach using simple circuit structures is most likely to bring success. We develop a suitable learning algorithm -- a continuous-time version of a temporal differential Hebbian learning algorithm for pulsed neural systems with non-linear synapses -- as well as circuits for the electronic implementation. Measurements from an experimental CMOS chip are presented. Finally, we use our test chip to solve simple classical conditioning tasks, thus verifying the design methodologies put forward in the paper.
|Journal||IEEE Transactions on Circuits and Systems II: analogue and digital signal processing|
|Publication status||Published - 1998|