Characterizing speed-independence of high-level designs

Michael Kishinevsky; Jørgen Staunstrup

doi:10.1109/ASYNC.1994.656285

Characterizing speed-independence of high-level designs

Michael Kishinevsky, Jørgen Staunstrup

Technical University of Denmark

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

This paper characterizes the speed-independence of high-level designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data types, and internal as well as external non-determinism. This makes it possible to verify the speed-independence of a design without providing an explicit realization of the environment. The verification can be done mechanically. A number of experimental designs have been verified including a speed-independent RAM, a complex switch of a data path, various Muller C-elements, FIFO registers, and counters

Original language	English
Title of host publication	Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems
Publisher	IEEE
Publication date	1994
Pages	44-53
ISBN (Print)	08-18-66210-7
DOIs	https://doi.org/10.1109/ASYNC.1994.656285
Publication status	Published - 1994
Event	International Symposium on Advanced Research in Asynchronous Circuits and Systems - Salt Lake City, UT, United States Duration: 3 Nov 1994 → 5 Nov 1994

Conference

Conference	International Symposium on Advanced Research in Asynchronous Circuits and Systems
Country/Territory	United States
City	Salt Lake City, UT
Period	03/11/1994 → 05/11/1994

Bibliographical note

Copyright: 1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "Characterizing speed-independence of high-level designs",

abstract = "This paper characterizes the speed-independence of high-level designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data types, and internal as well as external non-determinism. This makes it possible to verify the speed-independence of a design without providing an explicit realization of the environment. The verification can be done mechanically. A number of experimental designs have been verified including a speed-independent RAM, a complex switch of a data path, various Muller C-elements, FIFO registers, and counters",

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Kishinevsky, M & Staunstrup, J 1994, Characterizing speed-independence of high-level designs. in Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE, pp. 44-53, International Symposium on Advanced Research in Asynchronous Circuits and Systems, Salt Lake City, UT, United States, 03/11/1994. https://doi.org/10.1109/ASYNC.1994.656285

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N1 - Copyright: 1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1994

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AB - This paper characterizes the speed-independence of high-level designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data types, and internal as well as external non-determinism. This makes it possible to verify the speed-independence of a design without providing an explicit realization of the environment. The verification can be done mechanically. A number of experimental designs have been verified including a speed-independent RAM, a complex switch of a data path, various Muller C-elements, FIFO registers, and counters

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Y2 - 3 November 1994 through 5 November 1994

ER -

Characterizing speed-independence of high-level designs

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