Characterizing speed-independence of high-level designs

Michael Kishinevsky, Jørgen Staunstrup

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    Abstract

    This paper characterizes the speed-independence of high-level designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data types, and internal as well as external non-determinism. This makes it possible to verify the speed-independence of a design without providing an explicit realization of the environment. The verification can be done mechanically. A number of experimental designs have been verified including a speed-independent RAM, a complex switch of a data path, various Muller C-elements, FIFO registers, and counters
    Original languageEnglish
    Title of host publicationProceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems
    PublisherIEEE
    Publication date1994
    Pages44-53
    ISBN (Print)08-18-66210-7
    DOIs
    Publication statusPublished - 1994
    EventInternational Symposium on Advanced Research in Asynchronous Circuits and Systems - Salt Lake City, UT, United States
    Duration: 3 Nov 19945 Nov 1994

    Conference

    ConferenceInternational Symposium on Advanced Research in Asynchronous Circuits and Systems
    CountryUnited States
    CitySalt Lake City, UT
    Period03/11/199405/11/1994

    Bibliographical note

    Copyright: 1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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