Capacitor Mismatch Error Cancellation Technique for a
                Successive Approximation A/D Converter

Zhiliang Zheng; Un-Ku Moon; Jesper Steensgaard-Madsen; Bo Wang; Gabor C. Temes

Capacitor Mismatch Error Cancellation Technique for a Successive Approximation A/D Converter

Zhiliang Zheng
, Un-Ku Moon
, Jesper Steensgaard-Madsen
, Bo Wang
, Gabor C. Temes

Oregon State University

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

Abstract

An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated opamp is explained. SWITCAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1% 3 sigma nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.

Original language	English
Title of host publication	Proc. IEEE International Symposium on Circuits and Systems, vol. 2
Place of Publication	Piscataway
Publisher	IEEE
Publication date	1999
Pages	326-329
Publication status	Published - 1999
Event	1999 IEEE International Symposium on Circuits and Systems - Orlando, FL, United States Duration: 30 May 1999 → 2 Jun 1999 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6311

Conference

Conference	1999 IEEE International Symposium on Circuits and Systems
Country/Territory	United States
City	Orlando, FL
Period	30/05/1999 → 02/06/1999
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6311

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Cite this

@inproceedings{96d3bac9cd3e4888bd95f9b95e244523,

title = "Capacitor Mismatch Error Cancellation Technique for a Successive Approximation A/D Converter",

abstract = "An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50\% increase in conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated opamp is explained. SWITCAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1\% 3 sigma nominal capacitor mismatch, 10-20\% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.",

author = "Zhiliang Zheng and Un-Ku Moon and Jesper Steensgaard-Madsen and Bo Wang and Temes, \{Gabor C.\}",

year = "1999",

language = "English",

pages = "326--329",

booktitle = "Proc. IEEE International Symposium on Circuits and Systems, vol. 2",

publisher = "IEEE",

address = "United States",

note = "1999 IEEE International Symposium on Circuits and Systems ; Conference date: 30-05-1999 Through 02-06-1999",

url = "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6311",

}

Zheng, Z, Moon, U-K, Steensgaard-Madsen, J, Wang, B & Temes, GC 1999, Capacitor Mismatch Error Cancellation Technique for a Successive Approximation A/D Converter. in Proc. IEEE International Symposium on Circuits and Systems, vol. 2. IEEE, Piscataway, pp. 326-329, 1999 IEEE International Symposium on Circuits and Systems, Orlando, FL, United States, 30/05/1999.

Capacitor Mismatch Error Cancellation Technique for a Successive Approximation A/D Converter. / Zheng, Zhiliang; Moon, Un-Ku; Steensgaard-Madsen, Jesper et al.
Proc. IEEE International Symposium on Circuits and Systems, vol. 2. Piscataway: IEEE, 1999. p. 326-329.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

TY - GEN

T1 - Capacitor Mismatch Error Cancellation Technique for a Successive Approximation A/D Converter

AU - Zheng, Zhiliang

AU - Moon, Un-Ku

AU - Steensgaard-Madsen, Jesper

AU - Wang, Bo

AU - Temes, Gabor C.

PY - 1999

Y1 - 1999

N2 - An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated opamp is explained. SWITCAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1% 3 sigma nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.

AB - An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated opamp is explained. SWITCAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1% 3 sigma nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.

M3 - Article in proceedings

SP - 326

EP - 329

BT - Proc. IEEE International Symposium on Circuits and Systems, vol. 2

PB - IEEE

CY - Piscataway

T2 - 1999 IEEE International Symposium on Circuits and Systems

Y2 - 30 May 1999 through 2 June 1999

ER -