An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated opamp is explained. SWITCAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1% 3 sigma nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.
|Title of host publication||Proc. IEEE International Symposium on Circuits and Systems, vol. 2|
|Place of Publication||Piscataway|
|Publication status||Published - 1999|
|Event||1999 IEEE International Symposium on Circuits and Systems - Orlando, FL, United States|
Duration: 30 May 1999 → 2 Jun 1999
|Conference||1999 IEEE International Symposium on Circuits and Systems|
|Period||30/05/1999 → 02/06/1999|