Capacitor Mismatch Error Cancellation Technique for a Successive Approximation A/D Converter

Zhiliang Zheng, Un-Ku Moon, Jesper Steensgaard-Madsen, Bo Wang, Gabor C. Temes

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review


    An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated opamp is explained. SWITCAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1% 3 sigma nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.
    Original languageEnglish
    Title of host publicationProc. IEEE International Symposium on Circuits and Systems, vol. 2
    Place of PublicationPiscataway
    Publication date1999
    Publication statusPublished - 1999
    Event1999 IEEE International Symposium on Circuits and Systems - Orlando, FL, United States
    Duration: 30 May 19992 Jun 1999


    Conference1999 IEEE International Symposium on Circuits and Systems
    Country/TerritoryUnited States
    CityOrlando, FL
    Internet address

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