## Abstract

This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One closely mimics the BDD apply-operator while the other can exploit the structural information of the Boolean expression. The efficacy of the BED representation is demonstrated by verifying that the redundant and non-redundant versions of the ISCAS 85 benchmark circuits are identical. In particular, it is verified that the two 16-bit multiplication circuits (c6288 and c6288nr) implement the same Boolean functions. Using BEDs, this verification problem is solved in less than a second, while using standard BDD techniques this problem is infeasible. BEDs are useful in applications where the end-result as a reduced ordered BDD is small, for example for tautology checking

Original language | English |
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Title of host publication | Proceedings, Twelfth Annual IEEE Symposium on Logic in Computer Science, Warsaw, Poland |

Publisher | IEEE Computer Society Press |

Publication date | 1997 |

Pages | 88-98 |

ISBN (Print) | 0-8186-7925-5 |

DOIs | |

Publication status | Published - 1997 |

Event | Twelfth Annual IEEE Symposium on Logic in Computer Science - Warsaw, Poland Duration: 29 Jun 1997 → 2 Jul 1997 Conference number: 12 |

### Conference

Conference | Twelfth Annual IEEE Symposium on Logic in Computer Science |
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Number | 12 |

Country | Poland |

City | Warsaw |

Period | 29/06/1997 → 02/07/1997 |