Automatic Synthesis of Multilevel Combinational Logic

Anders C. Andersen; Jan Madsen; J.R. Madsen; H Pallisgaard

Automatic Synthesis of Multilevel Combinational Logic

Anders C. Andersen, Jan Madsen, J.R. Madsen, H Pallisgaard

Technical University of Denmark

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Abstract

This paper describes a system for the synthesis of multilevel combinational logic, transforming functional description into mask layout. The system includes a logic synthesis part, partly consisting of tools developed at Eindhoven University of Technology, which has been interfaced to the layout synthesis part in the CATOE-system, developed at the DesignCenter of Electronics Institute. The various steps in the transformation are presented together with a complete design example, implementing a multi-output combinational decoder function.

Original language	English
Title of host publication	Proceedings of the 15th European Solid-State Circuits Conference
Publisher	IEEE
Publication date	1989
Pages	109-112
ISBN (Print)	3-85403-101-7
Publication status	Published - 1989
Event	15th European Solid-State Circuits Conference - Vienna, Austria Duration: 20 Sept 1989 → 22 Sept 1989 Conference number: 15 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468015

Conference

Conference	15th European Solid-State Circuits Conference
Number	15
Country/Territory	Austria
City	Vienna
Period	20/09/1989 → 22/09/1989
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5468015

Bibliographical note

Copyright 1989 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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title = "Automatic Synthesis of Multilevel Combinational Logic",

abstract = "This paper describes a system for the synthesis of multilevel combinational logic, transforming functional description into mask layout. The system includes a logic synthesis part, partly consisting of tools developed at Eindhoven University of Technology, which has been interfaced to the layout synthesis part in the CATOE-system, developed at the DesignCenter of Electronics Institute. The various steps in the transformation are presented together with a complete design example, implementing a multi-output combinational decoder function.",

author = "Andersen, {Anders C.} and Jan Madsen and J.R. Madsen and H Pallisgaard",

note = "Copyright 1989 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.; 15th European Solid-State Circuits Conference, ESSCIRC '89. ; Conference date: 20-09-1989 Through 22-09-1989",

year = "1989",

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AU - Pallisgaard, H

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N2 - This paper describes a system for the synthesis of multilevel combinational logic, transforming functional description into mask layout. The system includes a logic synthesis part, partly consisting of tools developed at Eindhoven University of Technology, which has been interfaced to the layout synthesis part in the CATOE-system, developed at the DesignCenter of Electronics Institute. The various steps in the transformation are presented together with a complete design example, implementing a multi-output combinational decoder function.

AB - This paper describes a system for the synthesis of multilevel combinational logic, transforming functional description into mask layout. The system includes a logic synthesis part, partly consisting of tools developed at Eindhoven University of Technology, which has been interfaced to the layout synthesis part in the CATOE-system, developed at the DesignCenter of Electronics Institute. The various steps in the transformation are presented together with a complete design example, implementing a multi-output combinational decoder function.

M3 - Article in proceedings

SN - 3-85403-101-7

SP - 109

EP - 112

BT - Proceedings of the 15th European Solid-State Circuits Conference

PB - IEEE

T2 - 15th European Solid-State Circuits Conference

Y2 - 20 September 1989 through 22 September 1989

ER -

Automatic Synthesis of Multilevel Combinational Logic

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