Asynchronous design of Networks-on-Chip

Jens Sparsø

doi:10.1109/NORCHP.2007.4481080

Asynchronous design of Networks-on-Chip

Jens Sparsø (Invited author)

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or hundreds of (heterogeneous) IP-cores. The paper introduces the NoC concept, identifies a range of possible timing organizations (globally-synchronous, mesochronous, globally-asynchronous locally-synchronous and fully asynchronous), discusses the circuitry needed to implement these timing methodologies, and provides some implementation details for a couple of asynchronous NoCs designed at the Technical University of Denmark (DTU). The paper is written to support an invited talk at the NORCHIP’2007 conference.

Original language	English
Title of host publication	Proceedings of the 25th IEEE NORCHIP Conference 2007
Number of pages	4
Publisher	IEEE
Publication date	2007
ISBN (Print)	978-1-4244-1516-8
DOIs	https://doi.org/10.1109/NORCHP.2007.4481080
Publication status	Published - 2007
Event	2007 IEEE 25th NORCHIP Conference - Aalborg, Denmark Duration: 19 Nov 2007 → 20 Nov 2007 Conference number: 25 https://ieeexplore.ieee.org/xpl/conhome/4472911/proceeding

Conference

Conference	2007 IEEE 25th NORCHIP Conference
Number	25
Country/Territory	Denmark
City	Aalborg
Period	19/11/2007 → 20/11/2007
Internet address	https://ieeexplore.ieee.org/xpl/conhome/4472911/proceeding

Bibliographical note

Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "Asynchronous design of Networks-on-Chip",

abstract = "The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or hundreds of (heterogeneous) IP-cores. The paper introduces the NoC concept, identifies a range of possible timing organizations (globally-synchronous, mesochronous, globally-asynchronous locally-synchronous and fully asynchronous), discusses the circuitry needed to implement these timing methodologies, and provides some implementation details for a couple of asynchronous NoCs designed at the Technical University of Denmark (DTU). The paper is written to support an invited talk at the NORCHIP{\textquoteright}2007 conference.",

author = "Jens Spars{\o}",

note = "Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 2007 IEEE 25th NORCHIP Conference ; Conference date: 19-11-2007 Through 20-11-2007",

year = "2007",

doi = "10.1109/NORCHP.2007.4481080",

language = "English",

isbn = "978-1-4244-1516-8",

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AB - The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or hundreds of (heterogeneous) IP-cores. The paper introduces the NoC concept, identifies a range of possible timing organizations (globally-synchronous, mesochronous, globally-asynchronous locally-synchronous and fully asynchronous), discusses the circuitry needed to implement these timing methodologies, and provides some implementation details for a couple of asynchronous NoCs designed at the Technical University of Denmark (DTU). The paper is written to support an invited talk at the NORCHIP’2007 conference.

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DO - 10.1109/NORCHP.2007.4481080

M3 - Article in proceedings

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PB - IEEE

T2 - 2007 IEEE 25th NORCHIP Conference

Y2 - 19 November 2007 through 20 November 2007

ER -

Asynchronous design of Networks-on-Chip

Abstract

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