Asynchronous design of Networks-on-Chip

Jens Sparsø (Invited author)

    Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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    Abstract

    The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or hundreds of (heterogeneous) IP-cores. The paper introduces the NoC concept, identifies a range of possible timing organizations (globally-synchronous, mesochronous, globally-asynchronous locally-synchronous and fully asynchronous), discusses the circuitry needed to implement these timing methodologies, and provides some implementation details for a couple of asynchronous NoCs designed at the Technical University of Denmark (DTU). The paper is written to support an invited talk at the NORCHIP’2007 conference.
    Original languageEnglish
    Title of host publicationProceedings of the 25th IEEE NORCHIP Conference 2007
    Number of pages4
    PublisherIEEE
    Publication date2007
    ISBN (Print)978-1-4244-1516-8
    DOIs
    Publication statusPublished - 2007
    Event25th IEEE Norchip Conference - Aalborg, Denmark
    Duration: 19 Nov 200720 Nov 2007
    Conference number: 25

    Conference

    Conference25th IEEE Norchip Conference
    Number25
    CountryDenmark
    CityAalborg
    Period19/11/200720/11/2007

    Bibliographical note

    Copyright: 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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