ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality

Shankar Mahadevan; Michael Storgaard; Jan Madsen; Kashif Munir Virk

doi:10.1109/MASCOTS.2005.16

ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality

Shankar Mahadevan
, Michael Storgaard
, Jan Madsen
, Kashif Munir Virk

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

Designing complex heterogeneousmultiprocessor Systemon- Chip (MPSoC) requires support for modeling and analysis of the different layers i.e. application, operating system (OS) and platform architecture. This paper presents an abstract system-level modeling framework, called ARTS, to support the MPSoC designers in modeling the different layers and understanding their causalities. While others have developed tools for static analysis and modeled limited correlations (processor-memory or processor-communication), our model captures the impact of dynamic and unpredictable OS behaviour on processor, memory and communication performance. In particular, we focus on analyzing the impact of application mapping on the processor and memory utilization taking the on-chip communication latency into account. A case-study of real-time multimedia application consisting of 114 tasks on a 6-processor platform for a handheld terminal shows our frameworks co-exploration capabilities.

Original language	English
Title of host publication	13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)
Publisher	IEEE Computer Society Press
Publication date	2005
ISBN (Print)	0-7695-2458-3
DOIs	https://doi.org/10.1109/MASCOTS.2005.16
Publication status	Published - 2005
Event	13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems - Atlanta, United States Duration: 27 Sept 2005 → 29 Sept 2005 Conference number: 13 https://ieeexplore.ieee.org/xpl/conhome/10197/proceeding

Conference

Conference	13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Number	13
Country/Territory	United States
City	Atlanta
Period	27/09/2005 → 29/09/2005
Internet address	https://ieeexplore.ieee.org/xpl/conhome/10197/proceeding

Bibliographical note

Copyright: 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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@inproceedings{60dee3b6d20d4c759099aab685e39a15,

title = "ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality",

abstract = "Designing complex heterogeneousmultiprocessor Systemon- Chip (MPSoC) requires support for modeling and analysis of the different layers i.e. application, operating system (OS) and platform architecture. This paper presents an abstract system-level modeling framework, called ARTS, to support the MPSoC designers in modeling the different layers and understanding their causalities. While others have developed tools for static analysis and modeled limited correlations (processor-memory or processor-communication), our model captures the impact of dynamic and unpredictable OS behaviour on processor, memory and communication performance. In particular, we focus on analyzing the impact of application mapping on the processor and memory utilization taking the on-chip communication latency into account. A case-study of real-time multimedia application consisting of 114 tasks on a 6-processor platform for a handheld terminal shows our frameworks co-exploration capabilities.",

author = "Shankar Mahadevan and Michael Storgaard and Jan Madsen and Virk, \{Kashif Munir\}",

note = "Copyright: 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, MASCOTS 2005 ; Conference date: 27-09-2005 Through 29-09-2005",

year = "2005",

doi = "10.1109/MASCOTS.2005.16",

language = "English",

isbn = "0-7695-2458-3",

booktitle = "13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)",

publisher = "IEEE Computer Society Press",

url = "https://ieeexplore.ieee.org/xpl/conhome/10197/proceeding",

}

Mahadevan, S, Storgaard, M, Madsen, J & Virk, KM 2005, ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality. in 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer Society Press, 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, Atlanta, Georgia, United States, 27/09/2005. https://doi.org/10.1109/MASCOTS.2005.16

ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality. / Mahadevan, Shankar; Storgaard, Michael; Madsen, Jan et al.
13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer Society Press, 2005.

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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AB - Designing complex heterogeneousmultiprocessor Systemon- Chip (MPSoC) requires support for modeling and analysis of the different layers i.e. application, operating system (OS) and platform architecture. This paper presents an abstract system-level modeling framework, called ARTS, to support the MPSoC designers in modeling the different layers and understanding their causalities. While others have developed tools for static analysis and modeled limited correlations (processor-memory or processor-communication), our model captures the impact of dynamic and unpredictable OS behaviour on processor, memory and communication performance. In particular, we focus on analyzing the impact of application mapping on the processor and memory utilization taking the on-chip communication latency into account. A case-study of real-time multimedia application consisting of 114 tasks on a 6-processor platform for a handheld terminal shows our frameworks co-exploration capabilities.

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DO - 10.1109/MASCOTS.2005.16

M3 - Article in proceedings

SN - 0-7695-2458-3

BT - 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)

PB - IEEE Computer Society Press

T2 - 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

Y2 - 27 September 2005 through 29 September 2005

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ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality

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