Abstract
In this paper we explore the use of asynchronous routers in a time-division-multiplexed (TDM) network-on-chip (NOC), Argo, that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either synchronous or mesochronous.
We use asynchronous routers to achieve a simpler, smaller, and more robust, self-timed design. Our design exploits the fact that pipelined asynchronous circuits also behave as ripple FIFOs. Thus, it avoids the need for explicit synchronization FIFOs between the routers. Argo has interesting elastic timing properties that allow it to tolerate skew between the network interfaces (NIs).
The paper presents Argo NOC-architecture and provides a quantitative analysis of its ability of absorb skew between the NIs. Using a signal transition graph model and realistic component delays derived from a 65nm CMOS implementation, a worstcase analysis shows that a typical design can tolerate a skew of 1-5 cycles (depending on FIFO depths and NI clock frequency). Simulation results of a 2 x 2 NOC confirm this.
We use asynchronous routers to achieve a simpler, smaller, and more robust, self-timed design. Our design exploits the fact that pipelined asynchronous circuits also behave as ripple FIFOs. Thus, it avoids the need for explicit synchronization FIFOs between the routers. Argo has interesting elastic timing properties that allow it to tolerate skew between the network interfaces (NIs).
The paper presents Argo NOC-architecture and provides a quantitative analysis of its ability of absorb skew between the NIs. Using a signal transition graph model and realistic component delays derived from a 65nm CMOS implementation, a worstcase analysis shows that a typical design can tolerate a skew of 1-5 cycles (depending on FIFO depths and NI clock frequency). Simulation results of a 2 x 2 NOC confirm this.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2014 |
| Publisher | IEEE |
| Publication date | 2014 |
| Pages | 45-52 |
| ISBN (Electronic) | 978-1-4799-3789-9 |
| DOIs | |
| Publication status | Published - 2014 |
| Event | 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2014 - Postdam, Germany Duration: 12 May 2014 → 14 May 2014 Conference number: 20 http://www.async2014.org/ |
Conference
| Conference | 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) 2014 |
|---|---|
| Number | 20 |
| Country/Territory | Germany |
| City | Postdam |
| Period | 12/05/2014 → 14/05/2014 |
| Internet address |
| Series | International Symposium on Advanced Research in Asynchronous Circuits and Systems |
|---|---|
| ISSN | 1522-8681 |
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