Area-Efficiency Trade-Offs in Integrated Switched-Capacitor DC-DC Converters

Frederik Monrad Spliid; Dennis Øland Larsen; Arnold Knott

doi:10.1109/NORCHIP.2016.7792923

Area-Efficiency Trade-Offs in Integrated Switched-Capacitor DC-DC Converters

Frederik Monrad Spliid, Dennis Øland Larsen, Arnold Knott

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Abstract

This paper analyzes the relationship between efficiency and chip area in a fully integrated switched capacitor voltage divider dc-dc converter implemented in 180nm-technology and a 1/2 topology. A numerical algorithm for choosing the optimal sizes of individual components, in terms of power loss, based on the total chip area is developed. This algorithm also determines the optimal number of parallel phases in the converter, based on an estimate of power consumption in flip-
flop based clock circuits. By these means the maximum achievable efficiency as a function of chip area is estimated

Original language	English
Title of host publication	Proceedings of NORCAS 2016
Number of pages	5
Publisher	IEEE
Publication date	2016
ISBN (Print)	978-1-5090-1095-0
DOIs	https://doi.org/10.1109/NORCHIP.2016.7792923
Publication status	Published - 2016
Event	2016 IEEE Nordic Circuits and Systems Conference - Copenhagen, Denmark Duration: 1 Nov 2016 → 2 Nov 2016 Conference number: 2 https://ieeexplore.ieee.org/xpl/conhome/7784514/proceeding

Conference

Conference	2016 IEEE Nordic Circuits and Systems Conference
Number	2
Country/Territory	Denmark
City	Copenhagen
Period	01/11/2016 → 02/11/2016
Internet address	https://ieeexplore.ieee.org/xpl/conhome/7784514/proceeding

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Frederik Spliid SC paper v3Accepted author manuscript, 314 KB

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title = "Area-Efficiency Trade-Offs in Integrated Switched-Capacitor DC-DC Converters",

abstract = "This paper analyzes the relationship between efficiency and chip area in a fully integrated switched capacitor voltage divider dc-dc converter implemented in 180nm-technology and a 1/2 topology. A numerical algorithm for choosing the optimal sizes of individual components, in terms of power loss, based on the total chip area is developed. This algorithm also determines the optimal number of parallel phases in the converter, based on an estimate of power consumption in flip-flop based clock circuits. By these means the maximum achievable efficiency as a function of chip area is estimated",

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AB - This paper analyzes the relationship between efficiency and chip area in a fully integrated switched capacitor voltage divider dc-dc converter implemented in 180nm-technology and a 1/2 topology. A numerical algorithm for choosing the optimal sizes of individual components, in terms of power loss, based on the total chip area is developed. This algorithm also determines the optimal number of parallel phases in the converter, based on an estimate of power consumption in flip-flop based clock circuits. By these means the maximum achievable efficiency as a function of chip area is estimated

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DO - 10.1109/NORCHIP.2016.7792923

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T2 - 2016 IEEE Nordic Circuits and Systems Conference

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ER -

Area-Efficiency Trade-Offs in Integrated Switched-Capacitor DC-DC Converters

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