Area-Efficiency Trade-Offs in Integrated Switched-Capacitor DC-DC Converters

Frederik Monrad Spliid, Dennis Øland Larsen, Arnold Knott

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This paper analyzes the relationship between efficiency and chip area in a fully integrated switched capacitor voltage divider dc-dc converter implemented in 180nm-technology and a 1/2 topology. A numerical algorithm for choosing the optimal sizes of individual components, in terms of power loss, based on the total chip area is developed. This algorithm also determines the optimal number of parallel phases in the converter, based on an estimate of power consumption in flip-
flop based clock circuits. By these means the maximum achievable efficiency as a function of chip area is estimated
Original languageEnglish
Title of host publicationProceedings of NORCAS 2016
Number of pages5
Publication date2016
ISBN (Print)978-1-5090-1095-0
Publication statusPublished - 2016
Event2016 IEEE NorCAS Conference - Copenhagen, Denmark
Duration: 1 Nov 20162 Nov 2016


Conference2016 IEEE NorCAS Conference


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