Architecture Synthesis for Cost-Constrained Fault-Tolerant Flow-based Biochips

Morten Chabert Eskesen, Paul Pop, Seetal Potluri

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

Abstract

In this paper, we are interested in the synthesis of fault-tolerant architectures for flow-based microfluidic biochips, which use microvalves and channels to run biochemical applications. The growth rate of device integration in flow-based microfluidic biochips is scaling faster than Moore's law. This increase in fabrication complexity has led to an increase in defect rates during the manufacturing, thereby motivating the need to improve the yield, by designing these biochips such that they are fault tolerant. We propose an approach based on a Greedy Randomized Adaptive Search Procedure (GRASP) for the synthesis of fault-tolerant biochip architectures. Our approach optimizes the introduction of redundancy within a given unit cost budget, such that, the biochemical application can successfully complete its execution within its deadline, even in the presence of faults, and the yield is maximized. The proposed algorithm has been evaluated using several benchmarks and compared to the results of a Simulated Annealing metaheuristic.
Original languageEnglish
Title of host publicationProceedings of the 2016 Design, Automation and Test in Europe Conference & Exhibition (DATE)
PublisherIEEE
Publication date2016
Pages618-623
ISBN (Print)978-3-9815370-6-2
Publication statusPublished - 2016
Event19th Conference and Exhibition on Design, Automation and Test in Europe Conference and Exhibition (DATE 2016) - Dresden, Germany
Duration: 14 Mar 201618 Mar 2016
Conference number: 19
https://www.date-conference.com/

Conference

Conference19th Conference and Exhibition on Design, Automation and Test in Europe Conference and Exhibition (DATE 2016)
Number19
CountryGermany
CityDresden
Period14/03/201618/03/2016
Internet address

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