Analytical model and behavioral simulation approach for a ΣΔ fractional-N synthesizer employing a sample-hold element

Marco Cassia; Peter Jivan Shah; Erik Bruun

doi:10.1109/TCSII.2003.819138

Analytical model and behavioral simulation approach for a ΣΔ fractional-N synthesizer employing a sample-hold element

Marco Cassia, Peter Jivan Shah, Erik Bruun

Department of Electrical Engineering

Research output: Contribution to journal › Journal article › Research › peer-review

761 Downloads (Pure)

Abstract

A previously unknown intrinsic nonlinearity of standard SigmaDelta fractional-N synthesizers is identified. A general analytical model for SigmaDelta fractional-N phased-locked loops (PLLs) that includes the effect of the nonlinearity is derived and an improvement to the synthesizer topology is discussed. Also, a new methodology for behavioral simulation is presented: the proposed methodology is based on an object-oriented event-driven approach and offers the possibility to perform very fast and accurate simulations, and the theoretical models developed validate the simulation results. We show a GSM example to demonstrate the applicability of the simulation methodology to real study cases.

Original language	English
Journal	IEEE transactions on circuits and systems - 2, Analog and digital signal processing
Volume	50
Issue number	11
Pages (from-to)	850-859
ISSN	1057-7130
DOIs	https://doi.org/10.1109/TCSII.2003.819138
Publication status	Published - 2003

Bibliographical note

Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

Keywords

nonlinearities
phase noise
phase-locked loops
simulation
sigma-delta modulation
Linear systems

Access to Document

10.1109/TCSII.2003.819138

CassiaFinal published version, 562 KB

Fingerprint Dive into the research topics of 'Analytical model and behavioral simulation approach for a ΣΔ fractional-N synthesizer employing a sample-hold element'. Together they form a unique fingerprint.

Cite this

@article{693250cbabe34caabb91395e0e24b5ef,

title = "Analytical model and behavioral simulation approach for a ΣΔ fractional-N synthesizer employing a sample-hold element",

abstract = "A previously unknown intrinsic nonlinearity of standard SigmaDelta fractional-N synthesizers is identified. A general analytical model for SigmaDelta fractional-N phased-locked loops (PLLs) that includes the effect of the nonlinearity is derived and an improvement to the synthesizer topology is discussed. Also, a new methodology for behavioral simulation is presented: the proposed methodology is based on an object-oriented event-driven approach and offers the possibility to perform very fast and accurate simulations, and the theoretical models developed validate the simulation results. We show a GSM example to demonstrate the applicability of the simulation methodology to real study cases.",

keywords = "nonlinearities, phase noise, phase-locked loops, simulation, sigma-delta modulation, Linear systems",

author = "Marco Cassia and Shah, {Peter Jivan} and Erik Bruun",

note = "Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE",

year = "2003",

doi = "10.1109/TCSII.2003.819138",

language = "English",

volume = "50",

pages = "850--859",

journal = "IEEE transactions on circuits and systems - 2, Analog and digital signal processing",

issn = "1057-7130",

publisher = "IEEE",

number = "11",

}

Analytical model and behavioral simulation approach for a ΣΔ fractional-N synthesizer employing a sample-hold element. / Cassia, Marco; Shah, Peter Jivan; Bruun, Erik.

In: IEEE transactions on circuits and systems - 2, Analog and digital signal processing, Vol. 50, No. 11, 2003, p. 850-859.

Research output: Contribution to journal › Journal article › Research › peer-review

TY - JOUR

T1 - Analytical model and behavioral simulation approach for a ΣΔ fractional-N synthesizer employing a sample-hold element

AU - Cassia, Marco

AU - Shah, Peter Jivan

AU - Bruun, Erik

N1 - Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 2003

Y1 - 2003

N2 - A previously unknown intrinsic nonlinearity of standard SigmaDelta fractional-N synthesizers is identified. A general analytical model for SigmaDelta fractional-N phased-locked loops (PLLs) that includes the effect of the nonlinearity is derived and an improvement to the synthesizer topology is discussed. Also, a new methodology for behavioral simulation is presented: the proposed methodology is based on an object-oriented event-driven approach and offers the possibility to perform very fast and accurate simulations, and the theoretical models developed validate the simulation results. We show a GSM example to demonstrate the applicability of the simulation methodology to real study cases.

AB - A previously unknown intrinsic nonlinearity of standard SigmaDelta fractional-N synthesizers is identified. A general analytical model for SigmaDelta fractional-N phased-locked loops (PLLs) that includes the effect of the nonlinearity is derived and an improvement to the synthesizer topology is discussed. Also, a new methodology for behavioral simulation is presented: the proposed methodology is based on an object-oriented event-driven approach and offers the possibility to perform very fast and accurate simulations, and the theoretical models developed validate the simulation results. We show a GSM example to demonstrate the applicability of the simulation methodology to real study cases.

KW - nonlinearities

KW - phase noise

KW - phase-locked loops

KW - simulation

KW - sigma-delta modulation

KW - Linear systems

U2 - 10.1109/TCSII.2003.819138

DO - 10.1109/TCSII.2003.819138

M3 - Journal article

VL - 50

SP - 850

EP - 859

JO - IEEE transactions on circuits and systems - 2, Analog and digital signal processing

JF - IEEE transactions on circuits and systems - 2, Analog and digital signal processing

SN - 1057-7130

IS - 11

ER -