A previously unknown intrinsic nonlinearity of standard SigmaDelta fractional-N synthesizers is identified. A general analytical model for SigmaDelta fractional-N phased-locked loops (PLLs) that includes the effect of the nonlinearity is derived and an improvement to the synthesizer topology is discussed. Also, a new methodology for behavioral simulation is presented: the proposed methodology is based on an object-oriented event-driven approach and offers the possibility to perform very fast and accurate simulations, and the theoretical models developed validate the simulation results. We show a GSM example to demonstrate the applicability of the simulation methodology to real study cases.
|Journal||IEEE transactions on circuits and systems - 2, Analog and digital signal processing|
|Publication status||Published - 2003|
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- phase noise
- phase-locked loops
- sigma-delta modulation
- Linear systems