Abstract
Task Graphs is a commonly used application model in research in computer-aided design tools for design space exploration of embedded systems, including system synthesis, scheduling and application mapping. These design tools need an estimate of the actual communication in the target system caused by the application modelled by the task graph. In this paper, we present a method for analytically deriving the worst-case traffic pattern when a task graph is mapped to a multiprocessor system-on-chip with a shared memory architecture. We describe the additionally needed information besides the dependencies in the task graph in order to derive the traffic pattern. Finally, we construct a simulator that we use to find the actual traffic pattern in a system and compare this to the derived pattern. Results show that our worst-case derivation overestimates the bandwidth by 9% for systems with small caches and between 32% and 52% for systems with large caches.
Original language | English |
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Title of host publication | NORCHIP, 2009 |
Publisher | IEEE |
Publication date | 2009 |
Pages | 1-4 |
ISBN (Print) | 978-1-4244-4310-9 |
ISBN (Electronic) | 978-1-4244-4311-6 |
DOIs | |
Publication status | Published - 2009 |
Event | 2009 IEEE 27th NORCHIP Conference - Trondheim, Norway Duration: 16 Nov 2009 → 17 Nov 2009 Conference number: 27 https://ieeexplore.ieee.org/xpl/conhome/5374435/proceeding |
Conference
Conference | 2009 IEEE 27th NORCHIP Conference |
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Number | 27 |
Country/Territory | Norway |
City | Trondheim |
Period | 16/11/2009 → 17/11/2009 |
Internet address |