Analytical derivation of traffic patterns in cache-coherent shared-memory systems

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Abstract

This paper presents an analytical method to derive the worst-case traffic pattern caused by a task graph mapped to a cache-coherent shared-memory system. Our analysis allows designers to rapidly evaluate the impact of different mappings of tasks to IP cores on the traffic pattern. The accuracy varies with the application’s data sharing pattern, and is around 65% in the average case and 1% in the best case when considering the traffic pattern as a whole. For individual connections, our method produces tight worst-case bandwidths.
Original languageEnglish
JournalMicroprocessors and Microsystems
Volume35
Issue number7
Pages (from-to)632-642
ISSN0141-9331
DOIs
Publication statusPublished - 2011

Keywords

  • Traffic patterns
  • Shared-memory systems
  • Task graphs

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