Analysis and optimization of fault-tolerant embedded systems with hardened processors

Viacheslav Izosimov, Ilia Polian, Paul Pop

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    Abstract

    In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process reexecution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of reexecutions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.
    Original languageEnglish
    Title of host publicationAnalysis and optimization of fault-tolerant embedded systems with hardened processors
    Publication date2009
    Pages682-687
    ISBN (Print)978-1-4244-3781-8
    Publication statusPublished - 2009
    EventAutomation & Test in Europe Conference & Exhibition (DATE'09) - Nice, France
    Duration: 1 Jan 2009 → …

    Conference

    ConferenceAutomation & Test in Europe Conference & Exhibition (DATE'09)
    CityNice, France
    Period01/01/2009 → …

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