In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process reexecution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of reexecutions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.
|Title of host publication||Analysis and optimization of fault-tolerant embedded systems with hardened processors|
|Publication status||Published - 2009|
|Event||Automation & Test in Europe Conference & Exhibition (DATE'09) - Nice, France|
Duration: 1 Jan 2009 → …
|Conference||Automation & Test in Europe Conference & Exhibition (DATE'09)|
|Period||01/01/2009 → …|