Analysis and implementation of packet preemption for Time Sensitive Networks

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Abstract

A standard priority-queuing system is capable of arranging packets with different traffic classes to guarantee a relatively low latency for the high priority traffic. However, in practical cases, severe delay may be caused by starting a large, low-priority frame ahead of a time-critical frame. In this paper, interspersed express traffic is evaluated, which enables preemption of non-time-critical transmission, in particular, the preemptive queuing system allows the cut-through transmission for critical traffic and minimizes the jitter. We analyse the performance of packet preemption through a system level simulation in Riverbed Modeler. The simulation is complemented by numerical analysis which provides the average queuing delay for both types of traffic (preemptable and express). Furthermore, the paper describes an approach to implement the packet preemption solution on an FPGA in VHDL, which illustrates the complexity of hardware implementation.
Original languageEnglish
Title of host publication2017 IEEE 18th International Conference on High Performance Switching and Routing
Number of pages6
PublisherIEEE
Publication date2017
Pages1-6
ISBN (Print)978-1-5090-2839-9
DOIs
Publication statusPublished - 2017
Event2017 IEEE 18th International Conference on High Performance Switching and Routing - Convention Center of the State University of Campina, Campinas, Brazil
Duration: 18 Jun 201721 Jun 2017

Conference

Conference2017 IEEE 18th International Conference on High Performance Switching and Routing
LocationConvention Center of the State University of Campina
Country/TerritoryBrazil
CityCampinas
Period18/06/201721/06/2017
Series2017 Ieee 18th International Conference on High Performance Switching and Routing (hpsr)
ISSN2325-5609

Keywords

  • Delays
  • Numerical models
  • Time factors
  • Analytical models
  • Hardware
  • Mathematical model
  • Simulation
  • Time-sensitive network (TSN)
  • Packet preemption
  • Preemptive queuing
  • FPGA
  • VHDL
  • Riverbed modeler

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