Analysis and Design of Monolithic Inductors in Sub-micron CMOS

In the last few years the CMOS processes have gone into deep sub-micron channel lengths. This means that it is now possible to make GHz applications in CMOS. In analog GHz applications it is often necessary to have access to inductors. This report describes the development of a physical model of the planar inductors used in sub-micron CMOS. The model developed should be ofsuch a quality that it can be used for even very demanding circuits. The result of the model should be useable in all the normal circuit simulators used today. The model should furthermore be very fast in order to be useable for optimization. To verify the model more than 40 inductors have been produced and their performance have been measured. The produced inductors sweep a number of design parameters of the inductors, in order to get a realistic dataset. The produced inductors have inductances values of 2 nH to 10 nH, resonance frequencies of 200 MHz to 9 GHz and Q-values of 0.2 to 5. The comparison of the measured results and the results obtained using the model are very satisfying. The precision of parameters such as inductance, resonance frequency and Q-value are within a few percent, which is a very good result compared to other published work.