Analog capacitance ROM with IGFET bucket-brigade shift register

Erik Bruun; Ole Olesen

Analog capacitance ROM with IGFET bucket-brigade shift register

Erik Bruun, Ole Olesen

Department of Electrical Engineering

Research output: Contribution to journal › Journal article › Research › peer-review

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Abstract

A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.

Original language	English
Journal	I E E E Journal of Solid State Circuits
Volume	10
Issue number	1
Pages (from-to)	55-59
ISSN	0018-9200
Publication status	Published - 1975

Bibliographical note

Copyright: 1975 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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title = "Analog capacitance ROM with IGFET bucket-brigade shift register",

abstract = "A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.",

author = "Erik Bruun and Ole Olesen",

note = "Copyright: 1975 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE",

year = "1975",

language = "English",

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pages = "55--59",

journal = "I E E E Journal of Solid State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers",

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T1 - Analog capacitance ROM with IGFET bucket-brigade shift register

AU - Bruun, Erik

AU - Olesen, Ole

N1 - Copyright: 1975 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1975

Y1 - 1975

N2 - A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.

AB - A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.

M3 - Journal article

VL - 10

SP - 55

EP - 59

JO - I E E E Journal of Solid State Circuits

JF - I E E E Journal of Solid State Circuits

SN - 0018-9200

IS - 1

ER -