An SDRAM controller for real-time systems

Edgar Lakis, Martin Schoeberl

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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Abstract

For real-time systems we need to statically determine worst-case execution times (WCET) of tasks to proof the schedulability of the system. To enable static WCET analysis, the platform needs to be time-predictable. The platform includes the processor, the caches, the memory system, the operating system, and the application software itself. All those components need to be timing analyzable. Current computers use DRAM as a cost effective main memory. However, these DRAM chips have timing requirements that depend on former accesses and also need to be refreshed to retain their content. Standard memory controllers for DRAM memories are optimized to provide maximum bandwidth or throughput at the cost of variable latency for individual memory accesses. In this paper we present an SDRAM controller for realtime systems. The controller is optimized for the worst case and constant latency to provide a base of the memory hierarchy for time-predictable systems.
Original languageEnglish
Title of host publication2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)
Number of pages8
PublisherIEEE
Publication date2013
DOIs
Publication statusPublished - 2013
Event16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC - Paderborn, Germany
Duration: 19 Jun 201321 Jun 2013
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6906723

Conference

Conference16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC
CountryGermany
CityPaderborn
Period19/06/201321/06/2013
Internet address

Bibliographical note

2013 IEEE.Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Cite this

Lakis, E., & Schoeberl, M. (2013). An SDRAM controller for real-time systems. In 2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) IEEE. https://doi.org/10.1109/ISORC.2013.6913224
Lakis, Edgar ; Schoeberl, Martin. / An SDRAM controller for real-time systems. 2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) . IEEE, 2013.
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Lakis, E & Schoeberl, M 2013, An SDRAM controller for real-time systems. in 2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) . IEEE, 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC, Paderborn, Germany, 19/06/2013. https://doi.org/10.1109/ISORC.2013.6913224

An SDRAM controller for real-time systems. / Lakis, Edgar; Schoeberl, Martin.

2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) . IEEE, 2013.

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

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Lakis E, Schoeberl M. An SDRAM controller for real-time systems. In 2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC) . IEEE. 2013 https://doi.org/10.1109/ISORC.2013.6913224