An Implantable CMOS Amplifier for Nerve Signals

Jannik Hammel Nielsen, Torsten Lehmann

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    Abstract

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 5 nV/√Hz. The amplifier power consumption is 275 μW.
    Original languageEnglish
    Title of host publicationICECS 2001: 8th IEEE International Conference on Electronics, Circuits and Systems : Conference Proceedings
    Number of pages1183
    Volume1-3
    Publication date2001
    ISBN (Print)0-7803-7057-0
    DOIs
    Publication statusPublished - 2001
    Event2001 IEEE 8th International Conference on Electronics, Circuits and Systems - , Malta
    Duration: 2 Sep 20015 Sep 2001
    Conference number: 8
    https://ieeexplore.ieee.org/xpl/conhome/7591/proceeding

    Conference

    Conference2001 IEEE 8th International Conference on Electronics, Circuits and Systems
    Number8
    Country/TerritoryMalta
    Period02/09/200105/09/2001
    SponsorUniversity of Malta
    Internet address

    Bibliographical note

    Copyright: 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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