Abstract
This paper presents an area-efficient time-division-multiplexing (TDM) network-on-chip (NoC) intended for use in a multicore platform for hard real-time systems. In such a platform, a mode change at the application level requires the tear-down and set-up of some virtual circuits without affecting the virtual circuits that persist across the mode change. Our NoC supports such reconfiguration in a very efficient way, using the same resources that are used for transmission of regular data. We evaluate the presented NoC in terms of worst-case reconfiguration time, hardware cost, and maximum operating frequency. The results show that the hardware cost for an FPGA implementation of our architecture is a factor of 2.2 to 3.9 times smaller than other NoCs with reconfiguration functionalities, and that the worst-case time for a reconfiguration is shorter or comparable to those NoCs.
| Original language | English |
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| Title of host publication | Proceedings of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) |
| Number of pages | 4 |
| Publisher | IEEE |
| Publication date | 2016 |
| ISBN (Print) | 978-1-4673-9030-9 |
| DOIs | |
| Publication status | Published - 2016 |
| Event | 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) - Nara, Japan Duration: 31 Aug 2016 → 2 Sept 2016 Conference number: 10 http://www.arc.ics.keio.ac.jp/nocs16/program.html# |
Conference
| Conference | 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) |
|---|---|
| Number | 10 |
| Country/Territory | Japan |
| City | Nara |
| Period | 31/08/2016 → 02/09/2016 |
| Internet address |