Network interfaces (NIs) are used in multi-core systems where they connect processors, memories, and other IP-cores to a packet switched Network-on-Chip (NOC). The functionality of a NI is to bridge between the read/write transaction interfaces used by the cores and the packet-streaming interface used by the routers and links in the NOC. The paper addresses the design of a NI for a NOC that uses time division multiplexing (TDM). By keeping the essence of TDM in mind, we have developed a new area-efficient NI micro-architecture. The new design completely eliminates the need for FIFO buffers and credit based flow control - resources which are reported to account for 50–85% of the area in existing NI designs. The paper discusses the design considerations, presents the new NI micro-architecture, and reports area figures for a range of implementations.
|Title of host publication||2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)|
|Publication status||Published - 2013|
|Event||2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Grenoble, France|
Duration: 18 Mar 2013 → 22 Mar 2013
|Conference||2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)|
|Period||18/03/2013 → 22/03/2013|
|Series||Proceedings of the Design, Automation, and Test in Europe Conference and Exhibition|