An analog CMOS chip set for neural networks with arbitrary topologies

John Lansner; Torsten Lehmann

doi:10.1109/72.217186

An analog CMOS chip set for neural networks with arbitrary topologies

John Lansner
, Torsten Lehmann

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Abstract

An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 μs per layer

Original language	English
Journal	I E E E Transactions on Neural Networks
Volume	4
Issue number	3
Pages (from-to)	441-444
ISSN	1045-9227
DOIs	https://doi.org/10.1109/72.217186
Publication status	Published - 1993

Bibliographical note

Copyright: 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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@article{4467f916cd9a447da8e3d8613b35a88b,

title = "An analog CMOS chip set for neural networks with arbitrary topologies",

abstract = "An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 μs per layer",

author = "John Lansner and Torsten Lehmann",

note = "Copyright: 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE",

year = "1993",

doi = "10.1109/72.217186",

language = "English",

volume = "4",

pages = "441--444",

journal = "I E E E Transactions on Neural Networks",

issn = "1045-9227",

publisher = "IEEE Computational Intelligence Society",

number = "3",

}

TY - JOUR

T1 - An analog CMOS chip set for neural networks with arbitrary topologies

AU - Lansner, John

AU - Lehmann, Torsten

N1 - Copyright: 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 1993

Y1 - 1993

N2 - An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 μs per layer

AB - An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 μs per layer

U2 - 10.1109/72.217186

DO - 10.1109/72.217186

M3 - Journal article

C2 - 18267747

SN - 1045-9227

VL - 4

SP - 441

EP - 444

JO - I E E E Transactions on Neural Networks

JF - I E E E Transactions on Neural Networks

IS - 3

ER -

An analog CMOS chip set for neural networks with arbitrary topologies

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