An analog CMOS chip set for neural networks with arbitrary topologies

John Lansner, Torsten Lehmann

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    Abstract

    An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 μs per layer
    Original languageEnglish
    JournalI E E E Transactions on Neural Networks
    Volume4
    Issue number3
    Pages (from-to)441-444
    ISSN1045-9227
    DOIs
    Publication statusPublished - 1993

    Bibliographical note

    Copyright: 1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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