Coprocessors are frequently employed to extend the capabilities of a processor architecture which ultimately results in a performance boost. The concept is highly relevant in the context of hardware/software-codesign for specialized applications, especially when real-time requirements could normally not be met with pure software solutions. Moreover, the approach gives the opportunity to adapt an existing architecture in a modular way as well as reusing already available coprocessors. In this paper, we present an accelerator interface for the Patmos architecture. We outline how the interface is implemented and how the Patmos core is extended by it. Additionally, we demonstrate and evaluate the capabilities of the proposed design by benchmarking an SHA-256 coprocessor against software and hardware baselines. The coprocessor solution is more than 20 times faster than an implementation in software. Additionally, we assess the impact on hardware generation in terms of logic size and clock frequency. Our findings show that the presented design bears high potential for improving performance and alleviating the core's workload in comparison to IO devices and effectively subsumes their functionality for the purpose of hardware acceleration.
|Title of host publication||Proceedings of 2021 IEEE Nordic Circuits and Systems Conference|
|Number of pages||7|
|Publication status||Published - 2021|
|Event||2021 IEEE Nordic Circuits and Systems Conference - Virtuel event, Oslo, Norway|
Duration: 26 Oct 2021 → 27 Oct 2021
|Conference||2021 IEEE Nordic Circuits and Systems Conference|
|Period||26/10/2021 → 27/10/2021|