Real-time systems need time-predictable architectures to support static worst-case execution time (WCET) analysis. One architectural feature, the data cache, is hard to analyze when different data areas (e.g., heap allocated and stack allocated data) share the same cache. This sharing leads to less precise results of the cache analysis part of the WCET analysis. Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently. In this paper we present the design and implementation of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards timepredictable architectures.
|Title of host publication||2013 IEEE 16th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)|
|Number of pages||8|
|Publication status||Published - 2013|
|Event||16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC - Paderborn, Germany|
Duration: 19 Jun 2013 → 21 Jun 2013
|Conference||16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC|
|Period||19/06/2013 → 21/06/2013|