A system-level multiprocessor system-on-chip modeling framework

Kashif Munir Virk, Jan Madsen

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    We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework.
    Original languageEnglish
    Title of host publicationInternational Symposium on System-on-Chip, 2004. Proceedings.
    Publication date2004
    ISBN (Print)0-7803-8558-6
    Publication statusPublished - 2004
    EventInternational Symposium on System-on-Chip, 2004 -
    Duration: 1 Jan 2004 → …


    ConferenceInternational Symposium on System-on-Chip, 2004
    Period01/01/2004 → …

    Bibliographical note

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