A Spur-free Fractional-N Sigma-Delta PLL for GSM Applications: Linear Model and Simulations

Marco Cassia, Peter Jivan Shah, Erik Bruun

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

1081 Downloads (Pure)

Abstract

A new PLL topology and a new simplified linear model are presented. The new ΣΔ fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a Sample/Hold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
Original languageEnglish
Title of host publicationProceedings IEEE International Symposium on Circuits and Systems
PublisherIEEE
Publication date2003
Pages1065-1068
ISBN (Print)0-7803-7761-3
Publication statusPublished - 2003
Event2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 25 May 200328 May 2003
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570

Conference

Conference2003 IEEE International Symposium on Circuits and Systems
Country/TerritoryThailand
CityBangkok
Period25/05/200328/05/2003
Internet address

Bibliographical note

Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

Fingerprint

Dive into the research topics of 'A Spur-free Fractional-N Sigma-Delta PLL for GSM Applications: Linear Model and Simulations'. Together they form a unique fingerprint.

Cite this