Abstract
A new PLL topology and a new simplified linear model are presented. The new ΣΔ fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a Sample/Hold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
Original language | English |
---|---|
Title of host publication | Proceedings IEEE International Symposium on Circuits and Systems |
Publisher | IEEE |
Publication date | 2003 |
Pages | 1065-1068 |
ISBN (Print) | 0-7803-7761-3 |
Publication status | Published - 2003 |
Event | 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570 |
Conference
Conference | 2003 IEEE International Symposium on Circuits and Systems |
---|---|
Country | Thailand |
City | Bangkok |
Period | 25/05/2003 → 28/05/2003 |
Internet address |