A Spur-free Fractional-N Sigma-Delta PLL for GSM Applications: Linear Model and Simulations

Marco Cassia; Peter Jivan Shah; Erik Bruun

A Spur-free Fractional-N Sigma-Delta PLL for GSM Applications: Linear Model and Simulations

Marco Cassia, Peter Jivan Shah, Erik Bruun

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Article in proceedings › Research › peer-review

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Abstract

A new PLL topology and a new simplified linear model are presented. The new ΣΔ fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a Sample/Hold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.

Original language	English
Title of host publication	Proceedings IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Publication date	2003
Pages	1065-1068
ISBN (Print)	0-7803-7761-3
Publication status	Published - 2003
Event	2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003 http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570

Conference

Conference	2003 IEEE International Symposium on Circuits and Systems
Country	Thailand
City	Bangkok
Period	25/05/2003 → 28/05/2003
Internet address	http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570

Bibliographical note

Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

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Cite this

@inproceedings{6b0dd4638ff746179209e51ca5bb8bba,

title = "A Spur-free Fractional-N Sigma-Delta PLL for GSM Applications: Linear Model and Simulations",

abstract = "A new PLL topology and a new simplified linear model are presented. The new ΣΔ fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a Sample/Hold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.",

author = "Marco Cassia and Shah, {Peter Jivan} and Erik Bruun",

note = "Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE; 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",

year = "2003",

language = "English",

isbn = "0-7803-7761-3",

pages = "1065--1068",

booktitle = "Proceedings IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

address = "United States",

url = "http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8570",

}

TY - GEN

T1 - A Spur-free Fractional-N Sigma-Delta PLL for GSM Applications: Linear Model and Simulations

AU - Cassia, Marco

AU - Shah, Peter Jivan

AU - Bruun, Erik

N1 - Copyright: 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE

PY - 2003

Y1 - 2003

N2 - A new PLL topology and a new simplified linear model are presented. The new ΣΔ fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a Sample/Hold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.

AB - A new PLL topology and a new simplified linear model are presented. The new ΣΔ fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a Sample/Hold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.

M3 - Article in proceedings

SN - 0-7803-7761-3

SP - 1065

EP - 1068

BT - Proceedings IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -